Fujitsu F2MC-8L Family series Hardware Manual page 42

Peripherals
Address: 0012H CNTR
Address: 0013H COMR
HARDWARE CONFIGURATION
0 Values of counter and COMR do not match.
1 Values of counter and COMR match.
Note that 1 is always read when the Read Modify Write instruction is
executed.
The meaning of each bit to be written is as follows:
0 Clears this bit
1 Does not change this bit nor affect other bits
Note: In the PWM operation mode, neither the read nor write values of
these bits have any meaning.
[Bit 1] OE: Output signal control bit
When bit 1 is 1, the port serves as the PWM timer output. In the timer
operation mode, a signal that is reversed each time the values of the counter
and the compare register match is output. In the PWM operation mode, a
PWM signal is output.
0 General-purpose ports (P41)
1 Counter/PWM output pins (PWM)
Even if the DDR of P41 is set for input (bit 1 of DDR4 is set to 1), when this
bit is 1, it serves as the counter/PWM output pin.
[Bit 0] TIE: Interrupt enable bit (Timer mode)
If bit 0 is set to 1, an interrupt occurs when the values of the counter and
the compare register match.
0 Disables counter interrupt output
1 Enables counter interrupt output
However, in the PWM operation mode, an interrupt does not occur
irrespective of the value of this bits.
(b) Compare register (COMR)
This register holds the value to be compared with the counter value in the
timer operation mode, and also clears the counter when the value agrees
with the counter value. In the PWM operation mode, the High pulse width
can be specified by this register value.
Bit 7 Bit 6
Address: 0013
H
(W)
2– 27
Bit 5 Bit 4 Bit 3
(W) (W) (W) (W)
(Initial value)
XXXXXXXX
Bit 2 Bit 1 Bit 0
(W) (W) (W)
B