Fujitsu F2MC-8L Family series Hardware Manual page 107

(continued)
Address Read/Write
(R/W)
23
H
(R/W)
24
H
25
H
26
H
27
H
28
H
29
H
2A
H
2B
H
2C
H
2D
H
2E
H
2F
H
(R/W)
30
H
to 63
31
H H
(R/W)
to 78
64
H H
(R/W)
79
H
(R/W)
7A
H
7B
H
(W)
7C
H
(W)
7D
H
(W)
7E
H
—
7F
H
Note:— indicates the vacant area, it is not used
APPENDIX
Register
SIDR/SODR UART serial data register
SMC2 UART serial mode control register 2
EIC1 External interrupt 1 control register 1
VRAM Display data RAM
LCDR LCD control register
SEGR Segment output select register
ILR1 Interrupt level setting register 1
ILR2 Interrupt level setting register 2
ILR3 Interrupt level setting register 3
ITR Interrupt test register
App.– 4
Description of register