HARDWARE CONFIGURATION
(b) State transition diagram
CPU
SLEEP
Clock oscillates.
(9)
STOP
(7)
Clock stops.
(5)
(4)
RUN
(8)
Clock oscillates.
(3)
Oscillation stabilization
waiting
(1)
(2)
Power-on
(1) When power-on reset available selected
(2) When power-on reset unavailable selected
(3) After oscillation stabilizing
(4) Set STP bit to 1.
(5) Set SLP bit to 1.
(7) External reset when power-on reset unavailable selected
(8) External reset or interrupt when power-on reset available selected
(9) External reset or interrupt
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