Fujitsu F2MC-8L Family series Hardware Manual page 58

Peripherals
HARDWARE CONFIGURATION
[Bit 5] TDRE:
The TDRE flag is used to indicate the status of the serial output data register
(SODR).
0 Contains data
1 Empty
If SODR (Serial Output Data Register) is empty, and newly written data to
SODR, SODR will be driven out of the serial output pin (P44/SO).
When the TDRE flag is set to 1, a transmitter interrupt request is output.
[Bit 4] TIE: Transmitter interrupt request enable bit
Bit 4 is used to enable the transmitter interrupt request.
0 Disables interrupt
1 Enables interrupt
[Bit 3] RIE: Receiver interrupt request enable bit
Bit 3 is used to enable the receiver interrupt request.
0 Disables interrupt
1 Enables interrupt
[Bit 1] TD8/TP:
When parity is not provided, bit 1 is treated as bit 8 of the SODR register.
When parity is provided, this bit is used to determine whether the parity of
serial output data is even or odd.
0 Odd parity
1 Even parity
[Bit 0] RD8/RP:
When parity is not provided, bit 0 is treated as bit 8 of the SIDR register.
When parity is provided, this bit is used to determine whether the parity of
serial input data is even or odd (Initial value: undefined).
0 Odd parity
1 Even parity
2– 43
(Initial value)
(Initial value)
(Initial value)
(Initial value)