Fujitsu F2MC-8L Family series Hardware Manual page 54

Peripherals
Address: 0020 SMC1
H
Address: 0021 SRC
H
Address: 0022 SSD
H
Address: 0023 SIDR
H
Address: 0023 SODR
H
Address: 0024 SMC2
H
HARDWARE CONFIGURATION
(2) Register list
Address:
0020
H
Address:
0021
H
Address:
0022
H
Address:
0023
H
Address:
0023
H
Address:
0024
H
(3) Description of registers
(a) Serial mode control register 1 (SMC1)
This register is used to select the UART operation mode.
Bit 7 Bit 6
PEN SBL
Address: 0020
H
(R/W) (R/W)
[Bit 7] PEN: Parity enable
Bit 7 is used to determine whether to append a parity bit (when transmitting)
or to detect it (when receiving) for serial data input/output.
0 No parity
1 Parity
(Odd or even parity is set by TD8/TP of the SSD register.)
[Bit 6] SBL: Stop bit length
Bit 6 is used to determine the stop bit length of transmit data. At the receiving
end, only the first bit of the stop bit is recognized; second and later bits are
ignored.
0 2-bit length
1 1-bit length
2– 39
8 bits
R/W Serial mode control register 1
SMC1
R/W Serial rate control register
SRC
R/W Serial status and data register
SSD
R Serial input data register
SIDR
SODR W Serial output data register
SMC2
R/W Serial mode control register 2
Bit 5 Bit 4 Bit 3
MC1 MC0 SMDE
(R/W) (R/W) (R/W)
(Initial value)
00000-00
B
Bit 2 Bit 1 Bit 0
— SCKE SOE
(R/W) (R/W)
(Initial value)
(Initial value)