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Peripherals
HARDWARE CONFIGURATION
P40 to P46:
CMOS type I/O ports
(also used as peripheral input and output)
• Switching input and output
This port has a data-direction register (DDR) and a port-data register
(PDR) for each bit. Input and output can be set independently for each
bit. The pin with the DDR set to 1 is set to output, and the pin with the
DDR set to 0 is set to input. When the peripheral output bit is enabled,
these ports are set to output irrespective of the DDR setting conditions.
• Operation for output port (DDR = 1)
The value written at the PDR is output to the pin where the DDR is set
to 1. When the PDR is read, usually, the value of the pin is read instead
of the contents of the output latch. However, when the Read Modify Write
instruction is executed, the contents of the output latch are read
irrespective of the DDR setting conditions. Therefore, the bit-processing
instruction can be used even if input and output are mixed with each
other. When data is written to the PDR, the written data is held in the
output latch irrespective of the DDR setting conditions.
• Operation for input port (DDR = 0)
When used as the input port, the output impedance goes High.
Therefore, when the PDR is read, the value of the pin is read.
• Peripheral output operation
When using as the peripheral output, setting is performed by the
peripheral output enable bit (See the description of each peripheral). The
peripheral output enable bit has priority in switching input and output.
Even if the output from each peripheral is enabled, the read value of the
port is effective, so the peripheral output value can be checked.
• Peripheral input operation
The pin value at a port with the peripheral input function is always input
for the peripheral input irrespective of the setting of the DDR and
peripheral. Set the DDR to input when using an external signal for the
peripheral input.
• State when reset
When reset, the DDR is initialized to 0 and the output impedance goes
High at all bits. When reset, the PDR is not initialized. Therefore, set
the value of the PDR before setting the DDR to output.
• State in stop mode
With the SPL bit of the standby-control register set to 1, the output
impedance goes High in stop mode irrespective of the value of the DDR.
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