Fujitsu F2MC-8L Family series Hardware Manual page 85

Peripherals
Address: 000A TBCR
H
HARDWARE CONFIGURATION
(3) Description of registers
The detail of time-base timer control register (TBCR) is described below.
(a) Time-base timer control register (TBCR)
Bit 7
—
Address: 000A
H
[Bit 4] TBIE: Interval-timer interrupt enable bit
This bit is used to enable an interrupt by the interval timer.
Disables interval interrupt
0
Enables interval interrupt
1
[Bit 3] TBIF: Interval timer overflow bit
When writing, this bit is used to clear the interval timer overflow flag.
Clears interval timer overflow flag
0
No operation
1
When reading, this bit indicates that an interval timer overflow has occurred.
No interval timer overflow
0
Interval timer overflow
1
During Read Modify Write instruction, 1 is always read. If the TBIF bit is
set to 1 when the TBIE bit is 1, an interrupt request is output. This bit is
cleared upon reset.
[Bit 2] TBR: Time-base timer clear bit
This bit is used to clear time-base timer.
Clears time-base timer
0
No operation
1
This bit is always read 1.
[Bits 1 and 0] TBC1, TBC0: Interval time specification bits
These bits are used to specify interval timer cycle
.
TBC1 TBC0
0 0
0 1
1 0
1 1
2– 70
Bit 6 Bit 5 Bit 4 Bit 3
— — TBIE TBIF
(R/W) (R/W)
(Initial value)
XXX00000
B
Interval time
15
2 /f
CH
17
2 /f
CH
19
2 /f
CH
21
2 /f
CH
Bit 2 Bit 1 Bit 0
TBR TBC1 TBC0
(W) (R/W) (R/W)
Value at f = 5 MHz
CH
6.55 [ms]
26.21 [ms]
104.86 [ms]
0.42 [s]
f : clock frequency
CH