IBM Power Systems 775 Manual page 20

Architecture
PowerPC architecture
IEEE New P754 floating point compliant
Big endian, little endian, strong byte ordering support extension
46-bit real addressing, 68-bit virtual addressing
Off-chip bandwidth: 336 GBps:
– Local + remote interconnect)
Memory capacity: Up to 128 GBs per chip
Memory bandwidth: 128 GBps peak per chip
C1 core and cache
8 C1 processor cores per chip
2 FX, 2 LS, 4 DPFP, 1 BR, 1 CR, 1 VMX, 1 DFP
4 SMT, OoO
112x2 GPR and 172x2 VMX/VSX/FPR renames
PowerBus On-Chip Intraconnect
1.9 GHz Frequency
(8) 16 B data bus, 2 address snoop, 21 on/off ramps
Asynchronous interface to chiplets and off-chip interconnect
Differential memory controllers (2)
6.4-GHz Interface to Super Nova (SN)
DDR3 support max 1067 Mhz
Minimum Memory 2 channels, 1 SN/channel
Maximum Memory 8 channels X 1 SN/channel
2 Ports/Super Nova
8 Ranks/Port
X8b and X4b devices supported
PowerBus Off-Chip Interconnect
1.5 to 2.9 Gbps single ended EI-3
2 spare bits/bus
Max 256-way SMP
32-way optimal scaling
Four 8-B Intranode Buses (W, X, Y, or Z)
All buses run at the same bit rate
All capable of running as a single 4B interface; the location of the 4B interface within the
8 B is fixed
Hub chip attaches via W, X, Y or Z
Three 8-B Internode Buses (A, B,C)
C-bus multiplex with GX Only operates as an aggregate data bus (for example, address
and command traffic is not supported)
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IBM Power Systems 775 for AIX and Linux HPC Solution