IBM Power Systems 775 Manual page 21

Buses
Table 1-1 describes the POWER7 busses.
Table 1-1 POWER7 busses
Bus name
W, X, Y, Z
A,B
C
Mem1-Mem8
WXYZABC Busses
The off-chip PowerBus supports up to seven coherent SMP links (WXYZABC) by using
Elastic Interface 3 (EI-3) interface signaling that uses up to 3 Gbps. The intranode WXYZ
links up to four processor chips to make a 32way and connect a Hub chip to each processor.
The WXYZ links carry coherency traffic and data and are interchangeable as intranode
processor links or Hub links. The internode AB links connect up to two nodes per processor
chip. The AB links carry coherency traffic and data and are interchangeable with each other.
The AB links also are configured as aggregate data-only links. The C link is configured only
as a data-only link.
All seven coherent SMP links (WXYZABC) are configured as 8Bytes or 4Bytes in width.
The XYZABC Busses include the following features:
Four (WXYZ) 8-B or 4-B EI-3 Intranode Links
Two (AB) 8-B or 4-B EI-3 Internode Links or two (AB) 8-B or 4-B EI-3 data-only Links
One (C) 8-B or 4-B EI-3 data-only Link
PowerBus
The PowerBus is responsible for coherent and non-coherent memory access, IO operations,
interrupt communication, and system controller communication. The PowerBus provides all of
the interfaces, buffering, and sequencing of command and data operations within the storage
subsystem. The POWER7 chip has up to seven PowerBus links that are used to connect to
other POWER7 chips, as shown in Figure 1-2 on page 8.
The PowerBus link is an 8-Byte-wide (or optional 4-Byte-wide), split-transaction, multiplexed,
command and data bus that supports up to 32 POWER7 chips. The bus topology is a
multitier, fully connected topology to reduce latency, increase redundancy, and improve
concurrent maintenance. Reliability is improved with ECC on the external I/Os.
Data transactions are always sent along a unique point-to-point path. A route tag travels with
the data to help routing decisions along the way. Multiple data links are supported between
chips that are used to increase data bandwidth.
Width (speed) Connects
8B+8B with 2 extra bits Intranode processors
per bus (3 Gbps) & hub
8B+8B with 2 extra bits Other nodes within
per bus (3 Gbps) drawer
8B+8B with 2 extra bits Other nodes within
per bus (3 Gb/p) drawer
2B Read + 1B Write Processor to memory
with 2 extra bits per
bus (2.9 GHz)
Chapter 1. Understanding the IBM Power Systems 775 Cluster
Function
Used for address and
data
Data only
Data only, Multiplex
with Gx
7