IBM Power Systems 775 Manual page 23

Figure 1-3 Microprocessor core structural diagram
Reliability, availability, and serviceability features
The microprocessor core includes the following reliability, availability, and serviceability (RAS)
features:
POWER7 core:
– Instruction retry for soft core logic errors
– Alternate processor recovery for hard core errors detected
– Processor limited checkstop for other errors
– Protection key support for AIX
L1 I/D Cache Error Recovery and Handling:
– Instruction retry for soft errors
– Alternate processor recovery for hard errors
– Guarding of core for core and L1/L2 cache errors
L2 Cache:
– ECC on L2 and directory tags
– Line delete for L2 and directory tags (seven lines)
– L2 UE handling includes purge and refetch of unmodified data
– Predictive dynamic guarding of associated cores
L3 Cache:
– ECC on data
– Line delete mechanism for data (seven lines)
– L3UE handling includes purges and refetch of unmodified data
– Predictive dynamic guarding of associated cores for CEs in L3 not managed by the line
deletion
Chapter 1. Understanding the IBM Power Systems 775 Cluster
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