IBM Power Systems 775 Manual page 19

FSI
DIMM_1
FSI
DIMM_1
FSI
DIMM_2
FSI
DIMM_2
FSI
DIMM_3
FSI
DIMM_3
FSI
DIMM_4
FSI
DIMM_4
1B Write
2B Read
1B Write
2B Read
1B Write
2B Read
1B Write
2B Read
1B Write
2B Read
1B Write
2B Read
1B Write
2B Read
1B Write
2B Read
Figure 1-1 POWER7 chip block diagram
IBM POWER7 characteristics
This section provides a description of the following characteristics of the IBM POWER7 chip,
as shown in Figure 1-1:
240 GFLOPs:
– Up to eight cores per chip
– Four Floating Point Units (FPU) per core
– Two FLOPS/Cycle (Fused Operation)
– 246 GFLOPs = 8 cores x 3.84 GHz x 4 FPU x 2)
32 KBs instruction and 32 KBs data caches per core
256 KB L2 cache per core
4 MB L3 cache per core
Eight Channels of SuperNova buffered DIMMs:
– Two memory controllers per chip
– Four memory busses per memory controller (1 B wide Write, 2 B wide Read each)
CMOS 12S SOI 11 level metal
Die size: 567 mm2
.
Core Core Core Core
4 FXU, 4 FPU 4 FXU, 4 FPU 4 FXU, 4 FPU 4 FXU, 4 FPU
4T SMT 4T SMT 4T SMT 4T SMT
L2 L2 L2 L2
256KB 256KB 256KB 256KB
L3 L3 L3 L3
4MB 4MB 4MB 4MB
Fabric
p7
Chapter 1. Understanding the IBM Power Systems 775 Cluster
Core Core Core Core
4 FXU, 4 FPU 4 FXU, 4 FPU 4 FXU, 4 FPU 4 FXU, 4 FPU
4T SMT 4T SMT 4T SMT 4T SMT
L2 L2 L2 L2
256KB 256KB 256KB 256KB
L3 L3 L3 L3
4MB 4MB 4MB 4MB
OSC
OSC - A
OSC
OSC - B
TPMD
TPMD-A, TPMD-B
FSI
FSP1 - A
FSI
FSP1 - B
PSI
I2C
On Module SEEPRM
I2C
On Module SEEPRM
5