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Each hub chip ISR connects to four POWER7 chips via the HFI controller and the W busses.
The Torrent hub chip and its four POWER7 chips are called an
directly connected to seven other octants on a drawer via the wide on-planar L-Local busses
and to 24 other octants in three more drawers via the optical L-Remote busses.
Supernode
A
Supernodes are fully connected via the 16 optical D busses per hub chip. The ISR is
designed to support smaller systems with multiple D busses between Supernodes for higher
bandwidth and performance.
The ISR logically contains input and output buffering, a full crossbar switch, hierarchical route
tables, link protocol framers/controllers, interface controllers (HFI and PB data), Network
Management registers and controllers, and extensive RAS logic that includes link replay
buffers.
The Integrated Switch Router supports the following features:
Target cycle time up to 3 GHz
Target switch latency of 15 ns
Target GUPS: ~21 K. ISR assisted GUPs handling at all intermediate hops (not software)
Target switch crossbar bandwidth greater than 1 TB per second input and output:
– 96 Gbps WXYZ-busses (4 @ 24 Gbps) from P7 chips (unidirectional)
– 168 Gbps local L-busses (7 @ 24 Gbps) between octants in a drawer (unidirectional)
– 144 Gbps optical L-busses (24 @ 6 Gbps) to other drawers (unidirectional)
– 160 Gbps D-busses (16 @ 10 Gbps) to other Supernodes (unidirectional)
Two-tiered full-graph network
Virtual Channels for deadlock prevention
Cut-through Wormhole routing
Routing Options:
– Full hardware routing
– Software-controlled indirect routing by using hardware route tables
Multiple indirect routes that are supported for data striping and failover
Multiple direct routes by using LR and D-links supported for less than a full-up system
Maximum packet size that supported is 2 KB. Packets size varies from 1 to 16 flits, each flit
being 128 Bytes
Routing Algorithms:
– Round Robin: Direct and Indirect
– Random: Indirect routes only
IP Multicast with central buffer and route table and supports 256 Bytes or 2 KB packets
Global Hardware Counter implementation and support and includes link latency counts
LCRC on L and D busses with link-level retry support for handling transient errors and
includes error thresholds.
ECC on local L and W busses, internal arrays, and busses and includes Fault Isolation
Registers and Control Checker support
Performance Counters and Trace Debug support
16
IBM Power Systems 775 for AIX and Linux HPC Solution
is the fully interconnected collection of 32 octants in four drawers. Up to 512
octant
. Each ISR octant is
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