To find the nth assertion of a chip select line
Go to the timing analyzer's Trigger menu.
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Define the Edge1 term to represent the asserting transition on the
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chip select line.
You can rename the Edge1 term to make it correspond more closely to the
problem domain, for example, to CHIP_SEL.
Under Timing Sequence Levels, enter the following sequence
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specification:
•
TRIGGER on "CHIP_SEL" Occurs "10" Else on "no state" go to level "1"
You should use your value for "n" in place of "10" in the specification above.
Triggering on the 10th assertion of a chip select line
Single-Machine Trigger Examples
To find the nth assertion of a chip select line
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