HP 1660CS-Series User Manual page 123

Logic analyzers
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Configuration Capabilities
Table 7-2
Timing Analyzer Configurations
Mode
Conventional
half-channel
500 MHz
Conventional
full-channel
250 MHz
Transitional
half-channel
250 MHz
Transitional
full-channel
125 MHz
Glitch
half-channel
125 MHz
Timing Analyzer Configuration Considerations
Unused clock channels can be used as data channels.
In Glitch half-channel mode, memory is split between data and glitches.
7-4
HP 1660CS
HP 1661CS
8K-deep / 68
8K-deep / 51
chan. 65 data
chan. 48 data
+ 3 data or
+ 3 data or
clock
clock
4K-deep / 136
4K-deep / 102
chan. 130 data
chan. 96 data
+ 6 data or
+ 6 data or
clock
clock
8K-deep / 68
8K-deep / 51
chan. 65 data
chan. 48 data
+ 3 data or
+ 3 data or
clock
clock
4K-deep / 136
4K-deep / 102
chan. 130 data
chan. 96 data
+ 6 data or
+ 6 data or
clock
clock
4K-deep / 68
4K-deep / 51
chan. 65 data
chan. 48 data
+ 3 data or
+ 3 data or
clock
clock
HP 1662CS
HP 1663CS
8K-deep / 34
8K-deep / 17
chan. 32 data
chan. 16 data
+ 2 data or
+ 1 data or
clock
clock
4K-deep / 68
4K-deep / 34
chan. 64 data
chan. 32 data
+ 4 data or
+ 2 data or
clock
clock
8K-deep / 34
8K-deep / 17
chan. 32 data
chan. 16 data
+ 2 data or
+ 1 data or
clock
clock
4K-deep / 68
4K-deep / 34
chan. 64 data
chan. 32 data
+ 4 data or
+ 2 data or
clock
clock
4K-deep / 34
4K-deep / 17
chan. 32 data
chan. 16 data
+ 2 data or
+ 1 data or
clock
clock

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