Timing Analyzer; State Analyzer - HP 1660CS-Series User Manual

Logic analyzers
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The Trigger Sequence

Timing analyzer

Timing analyzer
When you configure a timing analyzer, the trigger sequence follows the
general outlines given previously. The trigger sequence of the timing analyzer
differs from the state analyzer in the following ways:
There are 10 levels available to build a trigger with.
The trigger term is always the last step.
The timing analyzer has two additional resources, Edge1 and Edge2.
Edge1 and Edge2 recognize occurrences of a glitch, rising edge, falling
edge, either edge, or no edge on a bit or ORed set of bits.

State analyzer

When you configure a state analyzer, the trigger sequence follows the general
outlines given previously. The trigger sequence of the state analyzer differs
from the timing analyzer in the following ways:
There are 12 levels available to build a trigger with.
The trigger term is never the last step.
The state analyzer cannot use Edge1 and Edge2.
9-18

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1662cs1663cs1660cs1661cs

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