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Status Registers
Use Status Registers to Determine the State of Analyzer Events and Conditions
Status Byte Register
Figure 2-4
Status Byte Register Diagram
The status byte register contains the following bits:
66
&
&
&
&
&
&
&
2
4
6
0
1
3
5
7
Bit
Decimal
Description
Value
0
1
Unused: This bit is always set to 0.
1
2
Unused: This bit is always set to 0.
2
4
Error/Event Queue Summery Bit: A 1 in this bit position
indicates that the SCPI error queue is not empty. The SCPI error
queue contains at least one error message.
3
8
Questionable Status Summary Bit: A 1 in this bit
position indicates that the questionable status summary bit has
been set. The questionable status event register can then be read
to determine the specific condition that caused this bit to be set.
4
16
Message Available (MAV): A 1 in this bit position
indicates that the analyzer has data ready in the output queue.
There are no lower status groups that provide input to this bit.
Status Byte Register
0
Unused
1
Unused
2
Error/Event Queue Summary Bit
3
Questionable
Status
Summary Bit
4
Message Available (MAV)
5
Standard Event Summary Bit
6
Request Service Summary (RQS)
7
Operation
Status
Summary Bit
+
Service Request Enable Register
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Chapter 2
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