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Service Request Enable Register - Agilent Technologies EMC Series Programmer's Manual

Spectrum analyzers 9 khz-1.5/3.0/6.7/13.2/26.5 ghz
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To query the status byte register, send the *STB command. The response will be
the decimal sum of the bits that are set to 1. For example, if bit number 7 and bit
number 3 are set to 1, the decimal sum of the 2 bits is 128 plus 8. So the decimal
value 136 is returned.

Service Request Enable Register

In addition to the status byte register, the status byte group also contains the service
request enable register. The status byte service request enable register lets you
choose which bits in the Status Byte Register will trigger a service request.
Send the *SRE <number> command (where <number> is the sum of the decimal
values of the bits you want to enable plus the decimal value of bit 6). For example,
assume that you want to enable bit 7 so that whenever the operation status
summary bit is set to 1, it will trigger a service request. Send the *SRE 192 (128 +
64) command. The *SRE? command returns the decimal value of the sum of the
bits enabled previously with the *SRE <number> command.
You must always add 64 (the numeric value of RQS bit 6) to your numeric sum
NOTE
when you enable any bits for a service request.
The service request enable register contains the following bits:
Chapter 2
Use Status Registers to Determine the State of Analyzer Events and Conditions
Bit
Decimal
Description
Value
5
32
Standard Event Status Summary Bit: A 1 in this bit
position indicates that the standard event status summary bit has
been set. The standard event status register can then be read to
determine the specific event that caused this bit to be set.
6
64
Request Service (RQS) Summery Bit: A 1 in this bit
position indicates that the analyzer has at least one reason to
report a status change. This bit is also called the master summary
status bit (MSS).
7
128
Operation Status Summary Bit: A 1 in this bit position
indicates that the operation status summary bit has been set. The
operation status event register can then be read to determine the
specific event that caused this bit to be set.
Status Registers
67

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