Questionable Frequency Positive Transition - Agilent Technologies EMC Series Programmer's Manual

Language Reference
STATus:QUEStionable Subsection

Questionable Frequency Positive Transition

:STATus:QUEStionable:FREQuency:PTRansition <integer>
:STATus:QUEStionable:FREQuency:PTRansition?
This command determines which bits in the Questionable Frequency Condition
register will set the corresponding bit in the Questionable Frequency Event register
when that bit has a positive transition (0 to 1). The variable <integer> is the sum of
the decimal values of the bits that you want to enable.
Factory Preset
and *RST:
Range:
Questionable Integrity Condition
:STATus:QUEStionable:INTegrity:CONDition?
This query returns the decimal value of the sum of the bits in the Questionable
Integrity Condition register.
The data in this register is continuously updated and reflects the current conditions.
NOTE
Questionable Integrity Enable
:STATus:QUEStionable:INTegrity:ENABle <integer>
:STATus:QUEStionable:INTegrity:ENABle?
This command determines which bits in the Questionable Integrity Condition
Register will set bits in the Questionable Integrity Event register, which also sets
the Integrity Summary bit (bit 9) in the Questionable Register. The variable
<integer> is the sum of the decimal values of the bits you want to enable.
Factory Preset
and *RST:
Range:
Questionable Integrity Event Query
:STATus:QUEStionable:INTegrity[:EVENt]?
This query returns the decimal value of the sum of the bits in the Questionable
Integrity Event register.
NOTE The register requires that the equivalent PTR or NTR filters be set before a
condition register bit can set a bit in the event register.
The data in this register is latched until it is queried. Once queried, the data is
cleared.
314
32767 (all 1's)
Integer, 0 to 32767
32767 (all 1's)
Integer, 0 to 32767
Chapter 5