Circuit Board Design Rules - ZiLOG Z8 User Manual

Z8 Microcontrollers
Clock

3.4.3 Circuit Board Design Rules

The following circuit board design rules are suggested:
• To prevent induced noise the crystal and load capacitors
should be physically located as close to the Z8® as possible.
• Signal lines should not run parallel to the clock oscillator
inputs. In particular, the crystal input circuitry and the internal
system clock output should be separated as much as possible.
C1
C2
Signals A B
(Parallel Traces
Must Be Avoided)
Signal C
(Connection to System Group
Must Be Avoided)
3-4
XTAL1
Z8
XTAL2
V
SS
Clock Generator Circuit
2
Z8
3
Figure 3-6. Circuit Board Design Rules
• V power lines should be separated from the clock oscillator
CC
input circuitry.
• Resistivity between XTAL1 or XTAL2 and the other pins
should be greater than 10 Mohms.
20 mm
max
1
2
3
Z8
Board Design Example
(Top View)
ZiLOG
Signal Line
Layout Should
Avoid High
Lighted Areas
V
SS
UM001601-0803