Introduction; Halt Mode Operation - ZiLOG Z8 User Manual

8.1 INTRODUCTION

In addition to the standard RUN mode, the Z8 MCU
two Power-Down modes to minimize device current consump-
tion. The two modes supported are HALT and STOP.

8.2 HALT MODE OPERATION

The HALT mode suspends instruction execution and turns off
the internal CPU clock. The on-chip oscillator circuit remains ac-
tive so the internal clock continues to run and is applied to the
Counter/Timer(s) and interrupt logic.
To enter the HALT mode, it is necessary to first flush the instruc-
tion pipeline to avoid suspending execution in mid-instruction.
To do this, the application program must execute a NOP instruc-
tion (opcode = FFH) immediately before the HALT instruction
(opcode 7FH), that is,
FF NOP ;clear the instruction pipeline
7F HALT ;enter HALT mode
The HALT mode is exited by interrupts, either externally or in-
ternally generated. Upon completion of the interrupt service rou-
tine, the user program continues from the instruction after
HALT.
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supports
The HALT mode may also be exited via a POR/RESET activa-
tion or a Watch-Dog Timer (WDT) timeout. (See the product
data sheet for WDT availability). In this case, program execution
will restart at the reset restart address 000CH.
To further reduce power consumption in the HALT mode, some
Z8 family devices allow dynamic internal clock scaling. Clock
scaling may be accomplished on the fly by reprogramming bit 0
and/or bit1 of the STOP-Mode Recovery register (SMR). See
Figure 8-1.
Note: Internal clock scaling directly effects Counter/Timer
operation — adjustment of the prescaler and downcounter values
may be required. To determine the actual HALT mode current
(I ) value for the various optional modes available, see the
CC1
related Z8 device's product specification.
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SER S ANUAL
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