Retriggerable Input Mode; Cascading Counter/Timers - ZiLOG Z8 User Manual

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6.5.4 Retriggerable Input Mode

The T Retriggerable Input Mode (TMR bits 5 and 4 are set to
IN
1) causes T1 to load and start counting on every occurrence of a
High-to-Low transition on T
IRQ5 will be generated if the programmed time interval (deter-
mined by T1 prescaler and counter/timer register initial values)
has elapsed since the last High-to-Low transition on T
gle-Pass Mode, the end-of-count resets the Enable Count bit.

6.6 CASCADING COUNTER/TIMERS

For some applications, it may be necessary to measure a time in-
terval greater than a single counter/timer can measure. In this
case, T and T can be used to cascade T0 and T1 as a single
IN OUT
unit (Figure 6-18). T0 should be configured to operate in Contin-
uous mode and to drive T
OUT
ternal clock input to T1 and wired back to T
T0 end-of-count, T undergoes a High-to-Low transition that
OUT
causes T1 to count.
÷ ÷
2
OSC
UM001601-0803
(Figure 6-17). Interrupt request
IN
. In Sin-
IN
. T should be configured as an ex-
IN
. On every other
OUT
4
PRE0 T0
Figure 6-18. Cascaded Counter / Timers
Subsequent T transitions will not cause T1 to load and start
IN
counting until software sets the Enable Count bit again. In Con-
tinuous Mode, counting continues once T1 is triggered until soft-
ware resets the Enable Count bit. When enabled, each High-to-
Low T transition causes T1 to reload and restart counting. In-
IN
terrupt request IRQ5 is generated on every end-of-count.
T1 can operate in either Single-Pass or Continuous mode. When
the T1 end-of-count is reached, interrupt request IRQ5 is gener-
ated. Interrupt requests IRQ2 (T
IRQ4 (T0 end-of-count) are also generated but are most likely of
no importance in this configuration and should be disabled.
÷
P3
2
6
T T
OUT
IRQ
4
Z8 Microcontrollers
High-to-Low transitions) and
IN
PRE1 T1
P3
1
IN
IRQ
2
Counter/Timers
IRQ
5
6-11