Reset; Reset Pin, Internal Por Operation - ZiLOG Z8 User Manual

4.1 RESET

This section describes the Z8 MCU
ing, and register initialization procedures. Reset is generated by
Power-On Reset (POR), Reset Pin, Watch-Dog Timer (WDT),
and Stop-Mode Recovery.
A system reset overrides all other operating conditions and puts
the Z8 into a known state. To initialize the chip's internal logic,
the RESET input must be held Low for at least 21 SCP or 5
XTAL clock cycles. The control register and ports are reset to
their default conditions after a POR, a reset from the RESET pin,
or Watch-Dog Timer timeout while in RUN mode and HALT

4.2 RESET PIN, INTERNAL POR OPERATION

In some cases, the Z8 hardware RESET pin initializes the control
and peripheral registers, as shown in Tables 4-1, 4-2, 4-3, and 4-
4. Specific reset values are shown by 1 or 0, while bits whose
states are unknown are indicated by the letter U. The Tables 4-1,
4-2, 4-3, and 4-4 show the reset conditions for the generic Z8.
UM001601-0803
C
HAPTER
R —W
ESET
®
reset conditions, reset tim-
4
-D T
ATCH OG IMER
mode. The control registers and ports are not reset to their default
conditions after Stop- Mode Recovery and WDT timeout while
in STOP mode.
While RESET pin is Low, AS is output at the internal clock rate,
DS is forced Low, and R//W remains High. The program counter
is loaded with 000CH. I/O ports and control registers are config-
ured to their default reset state.
Resetting the Z8 does not effect the contents of the general-
purpose registers.
Note: The register file reset state is device dependent. Please
refer to the selected device product specifications for register
availability and reset state.
U ' M
SER S ANUAL
4-1