Port 1; General I/O Mode - ZiLOG Z8 User Manual

ZiLOG

5.3 PORT 1

This section deals only with the I/0 operation. The port's external
memory interface operation is discussed later in this manual.
Figure 5-2 shows a block diagram of Port 1.

5.3.1 General I/O Mode

Port 1 can be an 8-bit, bidirectional, CMOS or TTL compatible
port with multiplexed Address (A7–A0) and Data (D7–D0)
ports. These eight I/O lines can be byte programmed as inputs or
outputs or can be configured under software control as an Ad-
dress/Data port for interfacing to external memory. The input
buffers can be Schmitt-triggered, level- shifted, or a single-point
buffer. In some cases, the output buffers can be globally pro-
grammed as either push-pull or open-drain. Low-EMI output
buffers can be globally programmed by software, as an OTP pro-
gram option, or as a ROM Mask Option. In some cases, the
Z8can have auto latches hardwired to the inputs. Please refer to
specific product specifications for exact input/output buffer-type
features available (Figures 5-7 and 5-8).
UM001601-0803
Register F8H (P01M)
Port 0-1 Mode Register (P01M)
(Write-Only)
D7 D6 D1 D0
P0 - P0 Mode
4 7
00 = Output
01 = Input
1X = A - A
12 15
Figure 5-5. Port 0 I/O Operation
Register F7H
Port 3 Mode Register (P3M)
(Write-Only)
D2
Figure 5-6. Port 0 Handshake Operation
Z8 Microcontrollers
I/O Ports
P0 - P0 Mode
0 3
00 = Output
01 = Input
1X = A - A
8 11
0 P3 = Input
2
P3 = Output
5
1 P3 = DAV0/RDY0
2
P3 = RDY0/DAV0
5
5-5