Triggered Input Mode - ZiLOG Z8 User Manual

Z8 Microcontrollers
Counter/Timers

6.5.3 Triggered Input Mode

The T Triggered Input Mode (TMR bits 5 and 4 are set to 1 and
IN
0, respectively) causes T1 to start counting as the result of an ex-
ternal event (Figure 6-17). T1 is then loaded and clocked by the
internal timer clock following the first High-to-Low transition
on the T input. Subsequent T
IN
the Single-Pass Mode, the Enable bit is reset whenever T1 reach-
es its end-of-count. Further T
÷
OSC
P3
T
1
IN
Trigger
6-10
transitions do not affect T1. In
IN
transitions will have no effect on
IN
Internal
2
Clock
Edge
Trigger
D D
Figure 6-17. Triggered Clock Mode
T1 until software sets the Enable Count bit again. In Continuous
mode, once T1 is triggered counting continues until software re-
sets the Enable Count bit. Interrupt request IRQ5 is generated
when T1 reaches its end-of-count.
TMR
D = 1
5
÷
4
TMR
D - D = 11
5 4
ZiLOG
PRE1 T1 IRQ
5
IRQ
2
UM001601-0803