ZiLOG Z8 PLUS User Manual
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ZiLOG Z8 PLUS User Manual

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  • Page 3 © 1999 by ZiLOG, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of ZiLOG, Inc. The information in this document is subject to change without notice. Devices sold by ZiLOG, Inc. are covered by warranty and patent indemnification provisions appearing in ZiLOG, Inc.
  • Page 5 The following conventions have been adopted to provide clarity and ease of use: Courier Font For Executables Commands, variables, icon names, entry field names, selection buttons, code examples, and other executable items are distinguished by the use of the Courier font. Where the use of the font is not possible, like in the Index, the name of the entity is capitalized.
  • Page 6 Â ADDITIONAL SOURCES OF INFORMATION In addition to this manual, you should have access to and be familiar with the following documentation: , UM95Z800103 Data Sheet for each product with which you work.

  • Page 7: Table Of Contents

    Chapter 1. Address Space Introduction ..........................1-1 Register File Space ........................1-1 General-Purpose Registers ....................1-5 Working Register Groups ..................... 1-6 Precautions .......................... 1-8 Control and Peripheral Registers ..................... 1-10 Control Registers ....................... 1-10 Peripheral Registers ......................1-10 Program Memory ........................1-11 Stack ............................
  • Page 8 Chapter 3. Instruction Set Functional Summary ........................3-1 Processor Flags .......................... 3-5 Condition Codes ......................... 3-7 Notation And Binary Encoding ....................3-10 Assembly Language Syntax ....................3-12 Z8Plus Instruction Summary ....................3-12 Opcode Map ........................3-18 Instruction Description and Formats ..................3-19 ADC–Add with Carry ......................
  • Page 9 JR–Jump Relative ......................3-50 LD–Load ..........................3-51 LDC–Load Constant ......................3-55 LDCI–Load Constant Auto Increment ................3-57 NOP–No Operation ......................3-59 OR–Logical OR ........................3-60 POP–Pop ........................... 3-62 PUSH–Push ........................3-63 RCF–Reset Carry Flag ...................... 3-64 RET–Return ........................3-65 RL–Rotate Left ........................3-66 RLC–Rotate Left Through Carry ..................
  • Page 10 IREQ Software Interrupt Generation ..................4-9 Vectored Processing ........................4-9 Nesting of Vectored Interrupts ................... 4-11 Polled Processing ........................4-12 Reset Conditions ........................4-12 Appendix A. Accessing the ZBBS/Internet Bulletin Board Information How to Access the ZBBS ZiLOG On The Internet Problem/Suggestion Report Form Index...
  • Page 11 Chapter 1. Address Space Figure 1-1. Complete Register File RAM Space ........1-2 Figure 1-2.
  • Page 12 Figure 4-6. Interrupt Request Register..........4-7 Figure 4-7.
  • Page 13 Chapter 1. Address Space Table 1-1 Z8 Core Control Registers ......... .1-3 Table 1-1 Page 0 Register File Organization .

  • Page 15: Introduction

    INTRODUCTION Two address spaces are available for the Z8 MCU: Register file RAM contains addresses for all the control registers and all the general purpose registers. Program memory contains addresses for all memory locations where executable code and/or data are stored. REGISTER FILE SPACE The on-chip register file RAM is organized into 16 pages, where each page has 256 addressable memory loca- tions.
  • Page 16 Â PAGES 1 THROUGH 15 CONTAIN GENERAL PURPOSE REGISTERS 256 THROUGH 4095 Control Registers General Purpose Registers (GPRs) Figure 1-1. Complete Register File RAM Space...
  • Page 17 Â Table 1-1. Z8 Core Control Registers Hex Address Register Name Register Description Comments 0FFH STKPTR (SPL) Stack Pointer Low LSB of Stack Pointer 0FEH Stack Pointer High MSB of Stack Pointer 0FDH REGPTR(RP) Register Pointer 0FCH FLAGS Flags 0FBH IMASK Interrupt Mask 1 Ints.
  • Page 18 Â Table 1-2. Page 0 Register File Organization Hex Address Range Register Description F0 - FF Core Control Registers E0 - EF Virtual Copy of the Current Working Register Set D0 - DF Port Logic Control Registers C0 -CF Timer Peripherals Control Registers B0 - BF Reserved for Future Extensions A0 - AF...

  • Page 19: General-Purpose Registers

    Â Rn+1 n = Even Address Figure 1-2. 16-Bit Register Addressing By using a logical instruction and a mask, individual bits within registers can be accessed for bit set, bit clear, bit complement, or bit test operations. For example, the instruction AND R15, MASK performs a bit clear operation.

  • Page 20: Working Register Groups

    Â Working Register Groups Instructions can access 8-bit registers and register pairs (16-bit words) using either 4-, 8-, or 12-bit address fields. Eight-bit address fields refer to the actual address of the register within the current page. For example, Register 58H is accessed by calling upon its 8-bit address, 01011000 (58H). The lower nibble of the Register Pointer specifies the current RAM page.
  • Page 21 Â Table 1-3. Working Register Groups (Continued) Register Pointer (FDH) Working Register Group High Nibble (Binary) (HEX) Actual Registers (HEX) 0110 60 - 6F 0101 50 - 5F 0100 40 - 4F 0011 30 - 3F 0010 20 - 2F 0001 10 - 1F 0000...

  • Page 22: Precautions

    Â The upper nibble of the register file address, provided by the register pointer, specifies The lower nibble specifies the current page of RAM. the active working-register group. R253 R7 R6 R5 R4 R3 R2 R1 R0 (Register Pointer) Working Register Group F The lower nibble of the register file address,...
  • Page 23 Â unexpected results if the hardware was in the process of decrementing the timer for the terminal count and generating an interrupt. The register space from 0E0H-0EFH is special. The MCU uses these addresses to flag accesses via 4-bit addressing mode to the current working register group. There are no physical registers at that location. Care must be taken that the Register Pointer never points at Group E on the first page (be loaded with E0H).

  • Page 24: Control And Peripheral Registers

    Â CONTROL AND PERIPHERAL REGISTERS Control Registers The standard control registers govern the operation of the CPU. Any instruction which references the register file can access these control registers. Available control registers are: Stack Pointer Low (SPL or STKPTR) Stack Pointer High (SPH) Register Pointer (RP or REGPTR) Flags (FLAGS) Interrupt Mask 1 (IMASK)

  • Page 25: Program Memory

    Â PROGRAM MEMORY The program memory map is shown in Figure 1-6. The first two bytes of program memory are reserved for the PC rollover vector. When the PC wraps around to 0000H, bytes 0000H and 0001H are executed as instructions, enabling a user defined behavior for this occurrence.
  • Page 26 Â Address On-chip ROM or EPROM Program Memory Decimal 65535 FFFF User Code Space Location of First Byte of Instruction Executed After RESET - IRQ (Available for Devices With Fewer Than 15 interrupts.) Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) PC Rollover Vector (Displacement) PC Rollover Vector (JR Instruction) Figure 1-6.

  • Page 27: Stack

    Â STACK The stack always resides in the general purpose registers of the on-chip register file RAM. The stack pointer register (SP) contains an address into the standard register file that is the address of the operand that is currently on the top of the stack. The register 0FFH is the 8-bit stack pointer (SP), that is used for all stack operations (see Figure 1-7).
  • Page 28 Â Prior value of Stack Pointer Prior value of Stack Pointer Top of Stack Top of Stack FLAGS Stack Contents Stack Contents After a Call After an Instruction Interrupt Cycle Figure 1-8. Stack Operations...

  • Page 29: Addressing Modes

    ADDRESSING MODES The Z8 microcontroller provides six addressing modes: Register (R) Indirect Register (IR) Indexed (X) Direct Address (DA) Relative Address (RA) Immediate Data (IM) With the exception of immediate data and condition codes, all operands are expressed as register file or Program Memory addresses.

  • Page 30: Register Addressing (R)

    Â In the following definitions of Z8 Addressing Modes, the use of register can also imply register pair, working register, or working register pair, depending on the context. NOTE: See the product data sheet for exact program and register memory types and address ranges available.

  • Page 31: Indirect Register Addressing (Ir)

    Â Register File Program Memory Points to Origin of Working Register Group Operand 4-Bit Working Registers Operand Points to Two Operand One Register OpCode Instruction in the (Example) Register File Figure 2-2. 4-Bit Register Addressing In 4-bit Register Addressing (see Figure 2-2), the destination and/or source addresses point to the Working Register within the current Working Register Group.
  • Page 32 Â Program Memory Register File Address of the Operand Used by the Instruction 8-Bit Register File Address Address Points to One Register in the One Operand Register File Instruction OpCode (Example) Points to the Register of the Operand Value Used in Operand Instruction Execution...

  • Page 33: Indexed Addressing (X)

    Â Register File Points to the Origin of the Working Program Memory Register Group Register Pair LSB 4-Bit Working Register Registers Address Pair MSB Points to the 16-Bit Address Instruction Example Working OpCode Points to Program Register References Memory Pair (Even Program Memory Program Address)
  • Page 34 Â Register File Points to the Working Register Points to the Origin of Working Register Group Program Memory Address Two Operand dst/ Offset Instruction OpCode Address Offset Value Used in the Instruction Operand Figure 2-5. Indexed Register Addressing...

  • Page 35: Direct Addressing (Da)

    Â DIRECT ADDRESSING (DA) The Direct Addressing mode, as shown in Figure 2-6, specifies the address of the next instruction to be executed. Only the Conditional Jump (JP) and Call (CALL) instructions use this addressing mode. Program Memory Program Memory Address Used Lower Addr.

  • Page 36: Relative Addressing (Ra)

    Â RELATIVE ADDRESSING (RA) In the Relative Addressing mode, illustrated in Figure 2-7, the instruction specifies a two’s-complement signed displacement in the range of –128 to +127. This is added to the contents of the Program Counter to obtain the address of the next instruction to be executed. The PC (prior to the add) consists of the address of the instruction following the Jump Relative (JR) or Decrement and Jump if Non-Zero (DJNZ) instruction.

  • Page 37: Immediate Data Addressing (Im)

    Â IMMEDIATE DATA ADDRESSING (IM) Immediate data is considered to be an addressing mode for the purposes of this discussion. It is the only addressing mode that does not indicate a register or memory address as the source operand. The operand value used by the instruction is the value supplied in the operand field itself.

  • Page 39: Functional Summary

    FUNCTIONAL SUMMARY instructions can be divided into the following eight functional groups: Load Arithmetic Logical Program Control Bit Manipulation Block Transfer Rotate and Shift CPU Control Table 3-1 through Table 3-8 show the instructions belonging to each group and the number of operands required for each.
  • Page 40 Â Table 3-1. Load Instructions Mnemonic Operands Instruction Clear dst, src Load dst, src Load Constant PUSH Push Table 3-2. Arithmetic Instructions Mnemonic Operands Instruction dst, src Add with Carry dst, src dst, src Compare Decimal Adjust Decrement DECW Decrement Word Increment INCW Increment Word...
  • Page 41 Â Table 3-4. Program Control Instructions Mnemonic Operands Instruction CALL Call Procedure DJNZ dst, src Decrement and Jump Non-Zero IRET Interrupt Return cc, dst Jump cc, dst Jump Relative Return Table 3-5. Bit Manipulation Instructions Mnemonic Operands Instruction dst, src Test Complement Under Mask dst, src...
  • Page 42 Â Table 3-7. Rotate and Shift Instructions Mnemonic Operands Instruction Rotate Left Rotate Left Through Carry Rotate Right Rotate Right Through Carry Shift Right Arithmetic SWAP Swap Nibbles Table 3-8. CPU Control Instructions Mnemonic Operands Instruction Complement Carry Flag Disable Interrupts Enable Interrupts HALT Halt...

  • Page 43: Processor Flags

    Â PROCESSOR FLAGS The Flag Register (FCH) informs the user of the processor’sbcurrent status. The flags and their bit positions in the Flag Register are shown in Figure 3-1. The Flag Register contains eight bits of status information which are set or cleared by CPU operations. Four of the bits (C, V, Z and S) can be tested for use with conditional Jump instructions.
  • Page 44 Â Sign Flag The Sign Flag stores the value of the most significant bit of a result following an arithmetic, logical, rotate, or shift operation. When performing arithmetic operations on signed numbers, binary two’s-complement notation is used to represent and process information.

  • Page 45: Condition Codes

    Â Watch- The Watch-Dog Timer reset flag is set by a watchdog timer timeout. This permits software to determine if a timeout of the Timer watchdog timer has occurred. (WDT) The WDT flag is cleared by the RESET pin. The WDT and SMR flags are the only flags effected by RESET.
  • Page 46 Â Table 3-10. Flag Settings Definitions Symbol Definition Cleared to 0 Set to 1 Set or cleared according to operation – Unaffected Undefined Table 3-11. Condition Codes Binary Mnemonic Definition Flag Settings 0000 Always False – 1000 (blank) Always True –...
  • Page 47 Â Table 3-11. Condition Codes (Continued) Binary Mnemonic Definition Flag Settings 0110 Equal Z = 1 1110 Not Equal Z = 0 1001 Greater Than or Equal (S XOR V) = 0 0001 Less Than (S XOR V) = 1 1010 Greater Than (Z OR (S XOR V)) = 0...

  • Page 48: Notation And Binary Encoding

    Â NOTATION AND BINARY ENCODING The operands and status flags use a notational shorthand. Operands, condition codes, address modes, and their notations are described in Table 3-12. Table 3-12. Notational Shorthand Notation Address Mode Operand Range* Condition Code See Table 3-11, condition codes Working Register n = 0 –...
  • Page 49 Â Table 3-13, which follows, describes additional symbols used. Table 3-13. Additional Symbols Symbol Definition Destination Operand Source Operand Indirect Address Prefix Stack Pointer Program Counter FLAGS Flag Register (FCH) Register Pointer (FDH) Interrupt Mask Register (FBH) Immediate Operand Prefix Hexadecimal Number Prefix Hexadecimal Number Suffix Binary Number Suffix...

  • Page 50: Assembly Language Syntax

    Â Assembly Language Syntax For proper instruction execution, assembly language syntax requires that the destination and source be spec- ified as dst, src (in that order). The following instruction descriptions show the format of the object code produced by the assembler. This binary format should be followed by users who prefer manual program coding or who intend to implement their own assembler.
  • Page 51 Â Table 3-14. Instruction Summary Address Mode Flags Affected op code Instruction and Operation Byte (Hex) ADC dst, src † 1[ ] dst ← dst + src +C ADD dst, src † 0[ ] dst ← dst + src AND dst, src †...
  • Page 52 Â Table 3-14. Instruction Summary (Continued) Address Mode Flags Affected op code Instruction and Operation Byte (Hex) – – – – – – IMR(7) ← 0 DJNZ, dst, src r RA – – – – – – dst ← dst – 1 (r = 0 –...
  • Page 53 Â Table 3-14. Instruction Summary (Continued) Address Mode Flags Affected op code Instruction and Operation Byte (Hex) LD dst, src – – – – – – dst ← src (r = 0 – F) LDC dst, src – – – –...
  • Page 54 Â Table 3-14. Instruction Summary (Continued) Address Mode Flags Affected op code Instruction and Operation Byte (Hex) RLC dst – – RR dst – – RRC dst – – SBC dst, src † 3[ ] dst ← dst – src – –...
  • Page 55 Â Table 3-15. Lower Nibble Values Address Mode Lower op code Nibble Figure 3-2, which follows, illustrates the Op Code map.

  • Page 56: Opcode Map

    Â OP CODE MAP LOWER NIBBLE (HEX) DJNZ r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, R2 r2, R1 r1, RA cc, RA r1, IM cc, DA r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, r2...

  • Page 57: Instruction Description And Formats

    12 Bits 16 Bits NOTE: The bytes shown in the boxes are in machine code order. The ZiLOG assembler always requires the format OPC, dst, src. Address modes R or IR can be used to specify a 4-bit working register. In this format, the source or destina- tion working-register operand is specified by adding 1110B (EH) to the High nibble of the operand.
  • Page 58 Â Add with Carry Instruction Format: ADC dst, src Address Mode OPC (Hex) Operation: dst ← dst + src + C The source operand, along with the setting of the Carry (C) Flag, is added to the destination operand. Two’s complement addition is performed.
  • Page 59 Â Add with Carry Example: Working register R3 contains 16H. The C flag is set to 1. Working register R11 contains 20H. The following statement leaves the value 37H in working register R3, and the C, Z, S, V, D, and H flags are set to 0. ADC R3, R11 Op Code: 12 3B.
  • Page 60 Â Add with Carry Example: Register 6CH contains 2AH. The C flag is not set. The following statement leaves the value 2DH in register 6CH. The C, Z, S, V, D, and H flags are set to 0. ADC 6CH, #03H Op Code: 16 6C 03 Example: Register D4H contains 5FH.

  • Page 61: Add-Add

    Â Instruction Format: ADD dst, src Address Mode OPC (Hex) Operation: dst ← dst + src The source operand is added to the destination operand. Two’s complement addition is performed. The sum is stored in the destination operand. The contents of the source operand are not changed. Flags: When the instruction is executed, the flags are set as follows: 1 if a value is carried from the most significant bit of the result;...
  • Page 62 Â Example: Working register R3 contains 16H. Working register R11 contains 20H. The following statement leaves the value 36H in working register R3. The C, Z, S, V, D, and H flags are set to 0. ADD R3, R11 Op Code: 02 3B Example: Working register R16 contains 16H.
  • Page 63 Â Logical AND Instruction Format: AND dst, src Address Mode OPC (Hex) Operation: dst ← dst AND src The source operand and the destination operandare processed with a logical AND operation. The result is a 1 stored whenever the corresponding bits in the two operands are both 1; otherwise, a 0 is stored. The result is stored in the destination operand.
  • Page 64 Â Logical AND Example: Working register R4 contains F9H (11111001B). Working register R13 contains 7BH. Register 7BH contains 6AH (01101010B). The following statement leaves the value 68H (01101000B) in working register R4. The Z, V, and S flags are set to 0. AND R4, @R13 Op Code: 53 4D Example: Register 3AH contains the value F5H (11110101B).
  • Page 65 Â CALL Call Procedure Instruction Format: CALL dst Address Mode OPC (Hex) Operation: SP ← SP - 2 @SP ← PC PC ← dst The Stack pointer (SP) is decremented by 2. The current contents of the program counter (PC) (the address of the first instruction following the CALL instruction) are pushed onto the top of the Stack.
  • Page 66 Â CALL Call Procedure Example: The contents of the PC are 1A47H and the contents of the SP (registers FEH and FFH) are 3002H. The following statements cause the SP to be decremented to 3000H, 1A4AH.The address following the CALL instructionis stored in external data memory at addresses 3000 and 3001H. The PC is loaded with 3521H and now points to the address of the first statement in the procedure to be executed.
  • Page 67 Â Complement Carry Flag Instruction Format: OPC (Hex) Operation: C ← NOT C The C flag is complemented. If C = 1, then it is changed to C = 0; or, if C = 0, then it is changed to C = 1. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction is complemented.

  • Page 68: Clr-Clear

    Â Clear Instruction Format: CLR dst Address Mode OPC (Hex) Operation: dst ← 0 The destination operand is set to 00H. Flags When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. The value set by the preceding instruction.
  • Page 69 Â Complement Instruction Format: COM dst Address Mode OPC (Hex) Operation: dst ← NOT dst The contents of the destination operand are complemented (one’s complement). All 1 bits are changed to 0, and all 0 bits are changed to 1. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.

  • Page 70: Cp-Compare

    Â Compare Instruction Format: CP dst, src Address Mode OPC (Hex) Operation: dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unchanged. Flags: When the instruction is executed, the flags are set as follows: 1 if a value is carried from the most significant bit of the result, otherwise, 0.
  • Page 71 Â Compare Example: Working register R3 contains 16H. Working register R11 contains 20H. The following statement sets the C and S flags to 1, and the Z and V flags are set to 0. CP R3, R1 Op Code: A2 3B Example: Working register R15 contains 16H.

  • Page 72: Decimal Adjust

    Â Decimal Adjust Instruction Format: DA dst Address Mode OPC (Hex) Operation: dst ← DA dst The destination operand is adjusted to two 4-bit BCD digits following a binary addition or subtraction opera- tion on BCD-encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), Table 3-14 indicates the operation performed.
  • Page 73 Â Decimal Adjust Flags: When the instruction is executed, the flags are set as follows: 1 if a value is carried or borrowed during the prior addition or subtaction. 1 if the result is 0; otherwise, 0. 1 if bit 7 of the result is 1 (negative); otherwise, 0. The value set by the preceding instruction.
  • Page 74 Â Decimal Adjust Example: A subtraction is performed on BCD values to subtract 17 from 25, the result should be 8. The result is incorrect when standard binary subtraction is performed on the binary representations of the BCD numbers. 0010 0101 = 25H 0001 0111 = 17H 0000 1110 = 0EH Register 45H contains the value 5FH.
  • Page 75 Â Decrement Instruction Format: DEC dst Address Mode OPC (Hex) Operation: dst ← dst - 1 The contents of the destination operand are decremented by one. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. 1 if the result is 0;...
  • Page 76 Â DECW Decrement Word Instruction Format: DECW dst Address Mode OPC (Hex) Operation: dst ← dst - 1 The contents of the destination (which must be an even address) operand are decremented by one. The desti- nation operand can be a Register Pair or a working register Pair. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.

  • Page 77: Di-Disable Interrupts

    Â Disable Interrupts Instruction Format: OPC (Hex) Operation: IMASK (7) ← 0 Bit 7 of control register FBH (the Interrupt Mask Register) is reset to 0. All interrupts are disabled, although they remain potentially enabled. For example, the Global Interrupt Enable is cleared, but not the individual interrupt level enables.
  • Page 78 Â DJNZ Decrement And Jump If Non-zero Instruction Format: DJNZ r, dst Address Mode OPC (Hex) (r=0 to F) Operation: r ← r - 1; If r ≠ 0, PC ← PC + dst The specified working register serves as a counter and is decremented. If the contents of the specified working register are not 0 after decrementing, then the relative address is added to the Program Counter (PC) and control passes to the statement whose address is now in the PC.
  • Page 79 Â DJNZ Decrement And Jump If Non-zero The assembly listing required for this routine is as follows: Assembly Op Code LD R6, #12 6E 0C LOOP: LD R9 %20(R6) C7 56 30 LD %14(R6), R9 D7 56 10 DJNZ R6, LOOP 6A F8...

  • Page 80: Ei-Enable Interrupts

    Â Enable Interrupts Instruction Format: OPC (Hex) Operation: IMASK (7) ← 1 Bit 7 of Control Register FBH (the Interrupt Mask Register) is set to 1. This allows potentially enabled inter- rupts to become enabled. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.

  • Page 81: Halt-Halt

    Â HALT Halt Instruction Format: HALT OPC (Hex) Operation: The HALT instruction turns off the internal CPU clock, but not the XTAL oscillation. The peripherals and interrupt logic remain active. Operation can be restarted by an interrupt or a reset. Flags: When the instruction is executed, the flags are set as follows The value set by the preceding instruction.

  • Page 82: Inc-Increment

    Â Increment Instruction Format: INC dst Address Mode OPC (Hex) r = 0–15 Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.
  • Page 83 Â Increment Example: Working register R10 contains 2AH. The following statement leaves the value 2BH in working register R10. The Z, V, and S flags are set to 0. INC R10 Op Code: AE Example: Register B3H contains CBH. The following statement leaves the value CCH in register CBH. The S flag is set to 1, and the Z and V flags are set to 0.
  • Page 84 Â INCW Increment Word Instruction Format: INCW dst Address Mode OPC (Hex) Operation: dst ← dst + 1 The contents of the destination (which must be an even address) operand is incremented by one. The destina- tion operand can be a Register Pair or a working register Pair. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.
  • Page 85 Â IRET Interrupt Return Instruction Format: IRET OPC (Hex) Operation: FLAGS ← @SP SP ← SP + 1 PC ← @SP SP ← SP + 2 IMR (7) ← 1 This instruction is issued at the end of an interrupt service routine. It restores the Flag Register (Control Register FCH) and the PC.

  • Page 86: Jp-Jump

    Â Jump Instruction Format: JP cc, dst Address Mode OPC (Hex) (cc = 0 to F) Operation: If condition code is true, then PC ← dst A conditional jump (JP) transfers program control to the destination address if the condition specified by cc is true.
  • Page 87 Â Jump Example: The Carry flag is 1. The following statement replaces the contents of the Program Counter with 1520H and transfers program control to that location. If the Carry flag had not been 1, control would have fallen through to the statement following the JP instruction. JP C, 1520H Op Code: 7D 15 20 Example:Working register pair RR2 contains the value 3F45H.
  • Page 88 Â Jump Relative Instruction Format: JR cc, dst Address Mode OPC (Hex) (cc=0 to F) Operation: If cc is true, PC ← PC + dst If the condition specified by the cc is true, the relative address is added to the PC and control passes to the instruction located at the address specified by the PC (See page 3-8 for a list of condition codes).
  • Page 89 Â Load Instruction Format: LD dst, src Address Mode OPC (Hex) r=0 to F *For OPC r9H, only a full 8-bit register can be used. The assember automatically uses the r8 Op Code for an instruction like: LD R0,R1.
  • Page 90 Â Load Operation: dst ← src The contents of the source operand are loaded into the destination operand. The contents of the source operand are not changed. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. The value set by the preceding instruction.
  • Page 91 Â Load Example: Working register R13 contains the value 45H. Working register R12 contains the value 00H. The following statement loads the value 00H into register 45H. The contents of working register R12 and working register R13 are not changed. LD @R13, R12 Op Code: F3 DC Example: Register 45H contains the value CFH.
  • Page 92 Â Load Example: Register 34H contains the value CFH. Register 45H contains the value FFH. The following state- ment loads the value FFH into register CFH. The contents of register 34H and register 45H are not changed. LD @34H, 45H Op Code: F5 45 34 Example: Working register R0 contains the value 08H.
  • Page 93 Â Load Constant Instruction Format: LDC dst, src Address Mode (Hex) Operation: dst ← src This instruction is used to load a byte constant from program memory into a working register, or vice versa. The address of the program memory location is specified by a working register pair. The contents of the source operand are not changed.
  • Page 94 Â Load Constant Example: Working register R2 contains the value 22H. Working register pair R6 and R7 contains the value 10A2H. The following statement loads the value 22H into program memory location 10A2H. The value of working register R2 is unchanged by the load. LDC @RR6, R2 Op Code: D2 26 NOTE: This instruction format is valid only for MCUs which can write to program memory.
  • Page 95 Â LDCI Load Constant Auto Increment Instruction Format: LDCI dst, src Address Mode (Hex) Operation: dst ← src r ← r + 1 rr ← rr + 1 This instruction is used for block transfers of data between program memory and the Register File. The address of the program memory location is specified by a working register Pair, and the address of the Register File location is specified by working register.
  • Page 96 Â LDCI Load Constant Auto-increment Example: Working register pair R6-R7 contains 30A2H, program memory location 30A2H and 30A3H contain 22H and BCH respectively, and working register R2 contains 20H. The following statement loads the value 22H into Register 20H. working register Pair RR6 is incremented to 30A3H and working register R2 is incremented to 21H.
  • Page 97 Â No Operation Instruction Format: OPC (Hex) Operation: No action is performed by this instruction. It is typically used for timing delays or clearing the pipeline. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. The value set by the preceding instruction.
  • Page 98 Â Logical OR Instruction Format: OR dst, src Address Mode OPC (Hex) Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination operand. The contents of the source operand are not changed. The OR operation stores a 1 bit whenever either of the corresponding bits in the two operands is a 1.
  • Page 99 Â Logical OR Example: Working register R1 contains 34H (00111000B). Working register R14 contains 4DH (10001101). The following statement leaves the value BDH (10111101B) in working register R1. The S flag is set to 1, and the Z and V flags are set to 0. OR R1, R14 Op Code: 42 1E Example: Working register R4 contains F9H (11111001B).
  • Page 100 Â Instruction Format: POP dst Address Mode OPC (Hex) Operation: dst ← @SP SP ← SP + 1 The contents of the location specified by the Stack Pointer (SP) are loaded into the destination operand. The SP is then incremented automatically. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.
  • Page 101 Â PUSH Push Instruction Format: PUSH src Address Mode OPC (Hex) Operation: SP ← SP - 1 @SP ← src The contents of the SP (stack pointer) are decremented by one. Then, the contents of the source operand are loaded into the location addressed by the updated SP, adding a new element to the stack. Flags :When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.
  • Page 102 Â Reset Carry Flag Instruction Format: OPC (Hex) Operation: C ← 0 The C flag is reset to 0, regardless of its previous value. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. The value set by the preceding instruction.
  • Page 103 Â Return Instruction Format: OPC (Hex) Operation: PC ← @SP SP ← SP + 2 This instruction is used to return from a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer (SP) are popped into the Program Control. The next statement executed is the one addressed by the new contents of the PC.
  • Page 104 Â Rotate Left Instruction Format: RL dst Address Mode OPC (Hex) Operation: C ← dst(7) dst(0) ← dst(7) dst(1) ← dst(0) dst(2) ← dst(1) dst(3) ← dst(2) dst(4) ← dst(3) dst(5) ← dst(4) dst(6) ← dst(5) dst(7) ← dst(6) The contents of the destination operand are rotated left by one bit position. The value from bit 7 is moved to the bit 0 position and also into the Carry flag.
  • Page 105 Â Rotate Left Example: The contents of register C6H are 88H (10001000B). The following statement leaves the value 11H (00010001B) in register C6H. The C and V flags are setto 1, and the S and Z flags are set to 0. RL C6H Op Code: 80 C6 Example: The contents of register C6H are 88H.
  • Page 106 Â Rotate Left Through Carry Instruction Format: RLC dst Address Mode OPC (Hex) Operation: ← dst(7) dst(0) ← C dst(1) ← dst(0) dst(2) ← dst(1) dst(3) ← dst(2) dst(4) ← dst(3) dst(5) ← dst(4) dst(6) ← dst(5) dst(7) ← dst(6) The contents of the destination operand along with the C flag are rotated left by one bit position.
  • Page 107 Â Rotate Left Through Carry Flags: When the instruction is executed, the flags are set as follows: 1 if the bit rotated from the most significant bit position was 1 (that is, bit 7 was previously set to 1 if the result is 0; otherwise, 0. 1 if bit 7 of the result is 1;...
  • Page 108 Â Rotate Right Instruction Format: RR dst Address Mode OPC (Hex) Operation: C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← dst(0) The contents of the destination operand are rotated to the right by one bit position. The initial value of bit 0 becomes the value of bit 7 and the C flag.
  • Page 109 Â Rotate Right Example: The contents of working register R6 are 31H (00110001B). The following statement leaves the value 98H (10011000B) in working register R6. The C, V, and S flags are set to 1, and the Z flag is set to 0. RR R6 Op Code: E0 E6 Example: The contents of register C6 are 31H.
  • Page 110 Â Rotate Right Through Carry Instruction Format: RRC dst Operation: Address Mode OPC (Hex) C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← C The contents of the destination operand with the C flag are rotated right by one bit position.
  • Page 111 Â Rotate Right Through Carry Flags: When the instruction is executed, the flags are set as follows: 1 if the bit rotated from the least significant bit position was 1 (that is, bit 0 was 1). 1 if the result is 0; otherwise, 0. 1 if bit 7 of the result is 1;...
  • Page 112 Â Subtract with Carry Instruction Format: SBC dst, src Address Mode OPC (Hex) Operation: dst ← dst - src - C The value of the source operand, and the value of the C flag, are subtracted from the destination operand. The result is stored in the destination operand.
  • Page 113 Â Subtract with Carry Example: Working register R3 contains 16H. The C flag is set to 1. Working register R11 contains 20H. The following statement leaves the value F5H in working register R3. The C, S, and D flags are set to 1, and the Z, V, and H flags are set to 0.
  • Page 114 Â Set Carry Flag Instruction Format: OPC (Hex) Operation: C ← 1 The C flag is set to 1, regardless of its previous value. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. The value set by the preceding instruction.
  • Page 115 Â Shift Right Arithmetic Instruction Format: SRA dst Address Mode OPC (Hex) Operation: C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← dst(7) An arithmetic right shift by one bit position is performed on the destination operand.
  • Page 116 Â Shift Right Arithmetic Example:The contents of working register R6 are 31H (00110001B). The following statement leaves the value 98H (00011000B) in working register R6. The C flag is set to 1, and the Z, V, and S flags are set to 0. SRA R6 Op Code: D0 E6 Example: Register C6 contains the value DFH.
  • Page 117 Â Set Register Pointer Instruction Format: SRP src Address Mod OPC (Hex) Operation: RP ← src The specified value is loaded into the Register Pointer (RP) Control Register (FDH). Bits 7-4 determine the working register group. Bits 3-0 selects the Memory Page. Addressing non-existent working register groups and memory pages results in undefined behavior.
  • Page 118 Â Set Register Pointer Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction. The value set by the preceding instruction. The value set by the preceding instruction. The value set by the preceding instruction. The value set by the preceding instruction.
  • Page 119 Â STOP Stop Instruction Format: STOP OPC (Hex) Operation: This instruction turns off the internal system clock (SCLK) and external crystal (XTAL) oscillator, and draws only standby current. The STOP mode is terminated by a RESET or Stop Mode Recovery (SMR) which causes the processor to restart the application program at address 0020H.
  • Page 120 Â Subtract Instruction Format: SUB dst, src Address Mode OPC (Hex) Operation: dst ← dst - src The source operand is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not changed. Subtraction is performed by adding the two’s complement of the source operand to the destination operand.
  • Page 121 Â Subtract Example: Working register R3 contains 16H. Working register R11 contains 20H. The following statement leaves the value F6H in working register R3. The C, S, and D flags are set to 1, and the Z, V, and H flags are set to 0.
  • Page 122 Â SWAP Swap Nibbles Instruction Format: SWAP dst Address Mode OPC (Hex) Operation: ↔ dst(7-4) dst(3-0) The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.
  • Page 123 Â Test Complement Under Mask Instruction Format: TCM dst, src Address Mode OPC (Hex) Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TCM instruction complements the destination operand, and then perforoms a logingal AND operation using ANDs with the mask (source operand).
  • Page 124 Â Test Complement Under Mask Example: Working register R14 contains the value F3H (11110011B). Working register R5 contains CBH. Register CBH contains 88H (10001000B) (bit 7 and bit 3 are tested if they are 1). The following statement resets the Z flag to 0, because bit 3 in the destination operand is not a 1. The V and S flags are also set to 0. TCM R14, @R5 Op Code: 63 E5 Example: Register D4H contains the value 04H (000001000B).
  • Page 125 Â Test Under Mask Instruction Format: TM dst, src Address Mode OPC (Hex) Operation: dst AND src This instruction tests selected bits in the destination operand for a logical 0 value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TM instruc- tion ANDs the destination operand with the mask (the source operand).
  • Page 126 Â Test Under Mask Example: Working register R14 contains the value F3H (11110011B). Working register R5 contains CBH. Register CBH contains 88H (10001000B) (bit 7 a bit 3 are tested if they are 0). The following statement resets the Z flag to 0, because bit 7 in the destination operand is not a 0. The S flag is set to 1, and the V flag is set to 0.
  • Page 127 Â Watch-Dog Timer Instruction Format: OPC (Hex) Operation: The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the device if it reaches its terminal count. Each execution of the WDT instruction refreshes the timer and prevents the WDT from timing out. Flags: When the instruction is executed, the flags are set as follows: The value set by the preceding instruction.
  • Page 128 Â Logical Exclusive OR Instruction Format: XOR dst, src Address Mode OPC (Hex) Operation: dst ← dst XOR src The source operand performs a logical EXCLUSIVE ORed operation, which stores a 1 in the destination operand whenever the corresponding bits in the two operands are different. The destination operand is set to 1;...
  • Page 129 Â Logical Exclusive OR Example: Working register R1 contains 38H (00111000B). Working register R14 contains 8DH (10001101B). The following statement leaves the value B5H (10110101B) in working register R1. The Z, and V flags are set to 0, and the S flag is set to 1. XOR R1, R14 Op Code: B2 1E Example: Working register R4 contains F9H (11111001B).
  • Page 131 INTRODUCTION The Z8 core allows 15 different interrupts from a variety of sources: external inputs on-chip peripherals software Interrupts can be masked by using the Interrupt Mask Register. All interrupts can be globally disabled by setting the master Interrupt Enable, bit 7 in the Interrupt Mask Register, to 0, with a Disable Interrupt (DI) instruction.
  • Page 132 Â The Z8 MCU family supports both vectored and polled interrupt handling. Details on vectored and polled interrupts can be found later in this chapter. IRQ7-IRQ14 IRQ0-IRQ6 Register Identifier IREQ2 IREQ 0FBH IMASK Interrupt Mask Interrupt Request 0FAH IREQ Interrupt Mask 2 0F9H IMASK2 Interrupt Request 2...
  • Page 133 Â INTERRUPT SOURCES Table 4-1 presents the interrupt types, sources, and vectors available in the Z8E001. Other processors from the Z8 family may define the interrupts differently. Table 4-1. Z8E001 Interrupt Types, Sources, and Vectors Vector Fixed Name Sources Location Comments Priority IREQ...
  • Page 134 Â Internal Interrupt Sources Internal interrupt sources and trigger conditions are device dependent. On-chip peripherals may set interrupt under various conditions. Some peripherals always set their corresponding IREQ bit while others must be specifically configured to do so. See the device product specification to determine available sources, triggering edge options, and exact programming details.
  • Page 135 Â Interrupt Mask Register (IMASK) Initialization The IMASK register individually or globally enables or disables the interrupts (see Figure 4-4). When bits 0 through bit 6 are set to 1, the corresponding interrupt requests are enabled. The IMASK2 register, bits 0 through 7, enable and disable IRQ7 through IRQ14, respectively.
  • Page 136 Â Figure 4-4. Interrupt Mask Register Interrupt Mask Register–IMASK (FBH) R/W R/W Reset R = Read W = Write X = Indeterminate U = Undefined/Undetermined Value Description Position Disables Interrupts Enables Interrupts Disables IRQ5 Enables IRQ5 Disables IRQ5 Enables IRQ5 Disables IRQ4 Enables IRQ4 Disables IRQ3...
  • Page 137 Â Figure 4-5. Interrupt Mask 2 Register Interrupt Mask 2 Register–IMASK2 (F9H) R/W R/W Reset R = Read W = Write X = Indeterminate U = Undefined/Undetermined Value Description Position Disables IRQ14 Enables IRQ14 Disables IRQ13 Enables IRQ13 Disables IRQ12 Enables IRQ12 Disables IRQ11 Enables IRQ11...
  • Page 138 Â Interrupt Request (IREQ) Register Initialization IREQ (see Figure 4-6) is a register that stores the interrupt requests for both vectored and polled interrupts. When an interrupt is issued, the corresponding bit position in the register is set to 1. Bit 0 to bit 5 are assigned to interrupt requests IREQ0 to IREQ5, respectively.
  • Page 139 Â Figure 4-7. Interrupt Request Register 2 Interrupt Request Register 2–IREQ2 (F8H) R/W R/W Reset R = Read W = Write X = Indeterminate U = Undefined/Undetermined Value Description Position IRQ14 reset IRQ14 set IRQ13 reset IRQ13 set IRQ12 reset IRQ12 set IRQ11 reset IRQ11 set...
  • Page 140 Â IREQ SOFTWARE INTERRUPT GENERATION IREQ can be used to generate software interrupts by specifying IREQ as the destination of any instruction referencing the Z8 Standard Register File. These software interrupts (SWI) are controlled in the same manner as hardware generated requests. In other words, the IMASK controls the enabling of each SWI. To generate a SWI, the request bit in IREQ is set by the following statement: OR IREQ,#NUMBER The immediate data variable, NUMBER, has a 1 in the bit position corresponding to the required level of SWI.
  • Page 141 Â Stack Pointer and Stack Stack Pointer and Stack Before an Interrupt After an Interrupt SP-3 Old Top of Stack Top of Stack PC LOW Byte PC HIGH Byte FLAGS Figure 4-8. Stacks Before and After Interrupt...
  • Page 142 Â Program Memory FFFFH Interrupt Service Routine Old PC Value 0020H Vector Selected By Priority Logic Interrupt Vector Table 0000H Figure 4-9. Interrupt Vector Table Location Nesting of Vectored Interrupts Nesting vectored interrupts allows higher priority requests to interrupt a lower priority request. To initiate vectored interrupt nesting, perform the following steps during the interrupt service routine: PUSH the old IMASK on the stack.
  • Page 143 Â POLLED PROCESSING Polled interrupt processing is supported by masking off the IREQ to be polled. This process is accomplished by setting the corresponding bits in the IMASK to 0. To initiate polled processing, check the appropriate bits in the IREQ using the Test Under Mask (TM) instruc- tion.
  • Page 145 BULLETIN BOARD INFORMATION The ZiLOG Bulletin Board Service (ZBBS) currently provides basic information on ZiLOG products and includes a ROM CODE upload area. In addition, the ZBBS provides valuable information on items of interest, such as ZiLOG specialty software and documentation.
  • Page 147 Host Computer Description/Type Campbell, CA 95008 Fax Number: (408) 558-8536 Email: tools@zilog.com Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
  • Page 149 bit set (OR) 3-3, 3-85 test complement under mask (TCM) 3-23 add (ADD) 3-3, 3-87 test under mask (TM) 3-20 add with carry (ADC) block diagram, interrupt addressing 12-bit 16-bit 3-27 call procedure (CALL) 4-bit address carry flag (C) 8-bit address 3-30 clear (CLR) direct...
  • Page 150 decimal adjust half-carry flag (H) 3-2, 3-34 3-43 DA instruction halt (HALT) flag high nibble decrement 3-40 and jump if non-zero (DJNZ) 3-37 DEC instruction immediate data addressing (IM) 3-38 word (DECW) 3-44 increment (INC) definitions 3-46 increment word (INCW) flag indexed addressing (X) flag settings...
  • Page 151 source 3-51 load overflow flag 3-55 constant (LDC) 3-3, 3-57 constant auto increment (LDCI) load instructions 1-10 peripheral registers 3-2, 3-30 clear (CLR) polled interrupt 3-2, 3-51 load (LD) 3-62 pop (POP) 3-2, 3-55 load constant (LDC) 3-2, 3-62 processor flags pop (POP) 3-2, 3-63 push (PUSH)
  • Page 152 3-4, 3-68 rotate left through carry (RLC) 3-4, 3-70 rotate right (RR) 3-4, 3-72 rotate right through carry (RRC) 3-4, 3-77 shift right arithmetic (SRA) 3-4, 3-84 swap nibbles (SWAP) 3-76 set carry flag (SCF) 3-79 set register pointer (SRP) 3-77 shift right arithmetic (SRA) 3-10...

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