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ZiLOG
6.4 T
MODES
OUT
The Timer Mode Register TMR (F1H) (Figure 6-9), is used in
conjunction with the Port 3 Mode Register P3M (F7H) (Figure
6-10) to configure P36 for T
der for T
to function, P36 must be defined as an output line
OUT
UM001601-0803
operation for T0 and T1. In or-
OUT
Register F1HR
Timer Mode Register (TMR)
(Read/Write)
D7 D6
D3
Figure 6-9. Timer Mode Register (T
Register F7H
Port 3 Mode Register (P3M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 P31 = Input (T
1 P31 = DAV2/RDY2 P36 = RDY2/DAV2
Figure 6-10. Port 3 Mode Register (T
by setting P3M bit 5 to 0. Output is controlled by one of the
counter/timers (T0 or T1) or the internal clock.
D0
0 = No Function
1 = Load T
0
0 = Disable T
Count
1
1 = Enable T
Count
1
T
Modes:
OUT
T
OFF = 00
OUT
T
OUT = 01
0
T
OUT = 10
1
Internal Clock OUT = 11
Operation)
OUT
)
P36 = Output (T
IN
OUT
Operation)
OUT
Z8 Microcontrollers
Counter/Timers
)
6-5

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