ZiLOG Z8 User Manual page 150

Z8 Microcontrollers
Instruction Set
12.5.1 Op Code Map
0 1
6.5 6.5
0
DEC DEC
R1 IR1
6.5 6.5
1 RLC RLC
R1 IR1
6.5 6.5
2
INC INC
R1 IR1
8.0 6.1
3
JP SRP
IRR1 IM
8.5 8.5
4
DA DA
R1 IR1
10.5 10.5
5
POP POP
R1 IR1
6.5 6.5
6 COM COM
R1 IR1
10/12.1 12/14.1
7
PUSH PUSH
R2 IR2
10.5 10.5
8
DECW DECW
RR1 IR1
6.5 6.5
9
RL RL
R1 IR1
10.5 10.5
A
INCW INCW
RR1 IR1
6.5 6.5
B CLR CLR
R1 IR1
6.5 6.5
C
RRC RRC
R1 IR1
6.5 6.5
D
SRA SRA
R1 IR1
6.5 6.5
E
RR RR
R1 IR1
8.5 8.5
F
SWAP SWAP
R1 IR1
Fetch
Cycles
Upper
Op Code
Nibble
First
Operand
12-10
2 3 4 5
6.5 6.5 10.5 10.5
ADD ADD ADD ADD
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
ADC ADC ADC ADC
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
SUB SUB SUB SUB
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
SBC SBC SBC SBC
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
OR OR OR OR
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
AND AND AND AND
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
TCM TCM TCM TCM
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
TM TM TM TM
r1, r2 r1, Ir2 R2, R1 IR2, R1
12.0
18.0
LDE
LDEI
r1, lrr2 lr1, lrr2
12.0 18.0
LDE
LDEI
r2, lrr1
lr2, lrr1
6.5 6.5 10.5 10.5
CP CP CP CP
r1, r2 r1, Ir2 R2, R1 IR2, R1
6.5 6.5 10.5 10.5
XOR XOR XOR XOR
r1, r2 r1, Ir2 R2, R1 IR2, R1
12.0 18.0
LDC LDCI
r1, Irr2 Ir1, Irr2
20.0
12.0 18.0
LDC LDCI CALL*
lrr1, r2
lrr1, Ir2 IRR1
6.5 10.5 10.5
LD LD LD
r1, IR2 R2, R1 IR2, R1
6.5 10.5
LD LD
Ir1, r2 R2, IR1
2 3
Lower
Op Code
Nibble
Pipeline
Cycles
4
10.5
CP Mnemonic
A
R , R1 2
Second
Operand
Lower Nibble (Hex)
6 7 8 9
10.5 10.5 6.5 6.5 12/10.5
ADD ADD LD LD
R1, IM IR1, IM r1, R2 r2, R1
10.5 10.5
ADC ADC
R1, IM IR1, IM
10.5 10.5
SUB SUB
R1, IM IR1, IM
10.5 10.5
SBC SBC
R1, IM IR1, IM
10.5 10.5
OR OR
R1, IM IR1, IM
10.5 10.5
AND AND
R1, IM IR1, IM
10.5 10.5
TCM TCM
R1, IM IR1, IM
10.5 10.5
TM TM
R1, IM IR1, IM
10.5 10.5
CP CP
R1, IM IR1, IM
10.5 10.5
XOR XOR
R1, IM IR1, IM
10.5
LD
r1,x,R2
20.0 10.5
CALL LD
DA r2,x,R1
10.5 10.5
LD LD
R1, IM IR1, IM
Bytes per Instruction
A B C D
12/10.0 6.5 12.10.0
DJNZ JR LD JP
r1, RA cc, RA r1, IM cc, DA
3
2
Legend:
R = 8-Bit Addr ess
r = 4-Bit Addr ess
R1 or r1 = Dst Addr ess
R2 or r2 = Sr c Addr ess
Sequence:
Opcode, First Operand,
Second Operand
Note: Blank areas ar e r eserved.
*2-byte instruction appears as
a 3-byte instruction
ZiLOG
E F
6.5
INC
r1
6.0
WDH
6.0
WDT
6.0
STOP
7.0
HAL T
6.1
DI
6.1
EI
14.0
RET
16.0
IRET
6.5
RCF
6.5
SCF
6.5
CCF
6.0
NOP
1
UM001601-0803