Page 1 Z8 M ICROCONTROLLER ’ ANUAL UM001601-0803...
Page 2 ©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica- tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
Page 3: Table Of Contents
RAM Protect ......................... 2-2 Working Register Groups ..................... 2-2 Error Conditions ........................2-4 Z8 Expanded Register File ....................... 2-5 Z8 Control And Peripheral Registers ..................2-8 Standard Z8 Registers ......................2-8 Expanded Z8 Registers ....................... 2-8 Program Memory ........................2-10 Z8 External Memory .........................
Page 4 Z8 Microcontrollers Table of Contents ZiLOG Chapter Title and Subsections Page Chapter 3. Clock (Continued) Oscillator Operation ........................3-3 Layout ..........................3-3 Indications of an Unreliable Design ..................3-3 Circuit Board Design Rules ....................3-4 Crystals and Resonators ...................... 3-5 LC Oscillator ..........................
Page 5 HALT Mode ........................5-29 STOP Mode ........................5-29 Open-Drain Configuration ......................5-30 Low EMI Emission ........................5-30 Input Protection ........................5-31 CMOS Z8 Auto Latches ......................5-32 Chapter 6. Counter/Timers Introduction ..........................6-1 Prescalers and Counter/Timers ....................6-2 Counter/Timer Operation ......................6-3 Load and Enable Count Bits ....................
Page 6 Z8 Microcontrollers Table of Contents ZiLOG Chapter Title and Subsections Page Vectored Processing ........................7-9 Vectored Interrupt Cycle Timing ..................7-11 Nesting of Vectored Interrupts ................... 7-12 Polled Processing ........................7-12 Reset Conditions ........................7-12 Chapter 8. Power-Down Modes Introduction ..........................8-1 HALT Mode Operation ........................
Page 7 Chapter 11. Addressing Modes Introduction ..........................11-1 Z8 Addressing Modes ......................11-1 Z8 Register Addressing (R) ...................... 11-2 Z8 Indirect Register Addressing (IR) ..................11-3 Z8 Indexed Addressing (X) ....................... 11-5 Z8 Direct Addressing (DA) ......................11-6 Z8 Relative Addressing (RA) ....................11-7 Z8 Immediate Data Addressing (IM) ..................
Page 8 viii UM001601-0803...
Page 9 ’ ANUAL IST OF IGURES Figure Title Page Chapter 1. Z8 MCU Product Overview Z8 MCU Block Diagram .......................1-2 Chap[ter 2. Address Space 16-Bit Register Addressing ......................2-2 Accessing Individual Bits (Example) ....................2-2 Working Register Addressing Examples ..................2-3 Register Pointer ...........................2-4 Expanded Register File Architecture ...................2-5...
Page 10 Reset Timing ..........................4-2 Example of External Power-On Reset Circuit ................4-3 Example of Z8 Reset with /RESET Pin, WDT, SMR, and POR ..........4-5 Example of Z8 Reset with WDT, SMR, and POR ................4-6 Example of Z8 Watch-Dog Timer Mode Register (Write-Only) ...........4-7 Example of Z8 with Simple SMR and POR .................4-8...
Page 11 Port 2 Configuration ........................5-30 Port Configuration Register (PCON) (Write-Only) ..............5-30 Diode Input Protection .......................5-31 OTP Diode Input Protection .......................5-31 Simplified CMOS Z8 I/O Circuit ....................5-32 Auto Latch Equivalent Circuit ..................5-33 Effect of Pulldown Resistors on Auto Latches ................5-33 Chapter 6. Counter/Timers Counter/Timer Block Diagram .....................6-1...
Page 12 Interrupt Request Register ......................7-7 IRQ Reset Functional Logic Diagram ..................7-8 Effects of an Interrupt on the STACK ..................7-9 Interrupt Vectoring ........................7-10 Z8 Interrupt Acknowledge Timing .....................7-11 Chapter 8. Power-Down Modes STOP-Mode Recovery Register (Write-Only Except Bit D7, Which Is Read-Only) ..............8-3 STOP-Mode Recovery Source ....................8-4...
Page 13 ZiLOG List of Figures Figure Title Page Chapter 10. External Interface Z8 External Interface Pins ......................10-1 External Address Configuration ....................10-3 Z8 Stack Selection ........................10-4 Port 3 Data Memory Operation ....................10-4 External Instruction Fetch or Memory Read Cycle ..............10-5 External Memory Write Cycle ....................10-6 Extended External Instruction Fetch or Memory Read Cycle ............10-7...
Page 14 Z8 Microcontrollers List of Figures ZiLOG Figure Title Page UM001601-0803...
Page 15 Z8 Standard Register File ......................2-1 Working Register Groups ......................2-3 ERF Bank Address ........................2-6 Z8 Expanded Register File Bank Layout ..................2-7 Expanded Register File Register Bank C, WR Group 0 ............. 2-8 Expanded Register File Bank 0, WR Group 0 ................2-9 Expanded Register File Bank F, WR Group 0 ................
Page 16 Z8 Microcontrollers List of Tables ZiLOG Table Title Page Chapter 8. Power-Down Modes STOP-Mode Recovery Source ....................8-4 Chaper 9. Serial I/O UART Register Map ........................9-2 Bit Rates ............................. 9-3 SPI Pin Configuration ......................... 9-8 UM001601-0803...
Page 17: Z8 Mcu Family Overview
Z8 MCU P RODUCT VERVIEW 1.1 Z8 MCU FAMILY OVERVIEW The ZiLOG Z8 microcontroller (MCU) product line continues to packaging options are available including plastic DIP, SOIC, expand with new product introductions. ZiLOG MCU products PLCC, and QFP. are targeted for cost-sensitive, high-volume applications includ- ®...
Page 18 Z8 Microcontrollers Z8 MCU Product Overview ZiLOG 1.1 Z8 MCU FAMILY OVERVIEW (Continued) Low-Power: CMOS with two standby modes; STOP and Full Z8 Instruction Set: Forty-eight basic instructions, • • HALT. supported by six addressing modes with the ability to operate on bits, nibbles, bytes, and words.
Page 19: Product Development Support
ZiLOG Z8 MCU Product Overview 1.1.2 Product Development Support The Z8 MCU product line is fully supported with a range of The Z86CCP01ZEM low-cost Z8 CCP™ real-time emula- cross assemblers, C compilers, ICEBOX emulators, single and tor/programmer kit was designed specifically to support all the gang OTP/EPROM programmers, and software simulators.
Page 21: Introduction
2.2 Z8 MCU STANDARD REGISTER FILE The Z8 Standard Register File totals up to 256 consecutive bytes Table 2-1. Z8 Standard Register File (Registers). The register file consists of 4 I/O ports (00H-03H),...
Page 22: General-Purpose Registers
MASK performs a bit clear operation. Figure 2-2 shows this ex- ample. 2.2.3 Working Register Groups Z8 instructions can access 8-bit registers and register pairs (16- bit words) using either 4-bit or 8-bit address fields. 8-bit address fields refer to the actual address of the register. For example, Register 58H is accessed by calling upon its 8-bit binary equiv- alent, 01011000 (58H).
Page 23 Z8 Microcontrollers ZiLOG Address Space Table 2-2. Working Register Groups Register Pointer Working Actual (FDH) Register Group Registers High Nibble (HEX) (HEX) 1111(B) F0–FF 1110(B) E0–EF 1101(B) D0–DF 1100(B) C0–CF 1011(B) B0–BF 1010(B) A0–AF 1001(B) 90–9F 1000(B) 80–8F 0111(B) 70–7F 0110(B) 60–6F...
Page 24: Error Conditions
Note: The full register file is shown. Please refer to the selected device product specification for actual file size. 2.2.4 Error Conditions Registers in the Z8 Standard Register File must be correctly used Writing to bits that are defined as timer output, serial output, •...
Page 25: Z8 Expanded Register File
Address Space 2.3 Z8 EXPANDED REGISTER FILE The standard register file of the Z8 has been expanded to form Standard Register File) that can then be divided into 16 Working 16 Expanded Register File (ERF) Banks (Figure 2-5). Each ERF Register Groups.
Page 26 0010(B) Expanded Register File Bank 2 0011(B) Expanded Register File Bank 3 For example, if ERF Bank C is selected, the Z8 Standard Regis- 0100(B) Expanded Register File Bank 4 ters 00H through 0FH are no longer accessible. Registers 00H...
Page 27 Note: When an ERF Bank other than Bank 0 is enabled, the first (Reserved) 16 bytes of the Z8 Standard Register File (I/O ports 0 to 3, Groups 4 to F) are no longer accessible (the selected ERF Bank, 2(H) Not Implemented Registers 00H to 0FH are accessed instead).
Page 28: Z8 Control And Peripheral Registers
Function Register • Stack Pointer Low-Byte (SPL) Reserved Reserved The Z8 uses a 16-bit Program Counter (PC) to determine the se- quence of current program instructions. The PC is not an addres- Reserved sable register. Reserved Reserved Peripheral registers are used to transfer data, configure the oper- Reserved ating mode, and control the operation of the on-chip peripherals.
Page 29 Working Register Group 0 in ERF Bank 0 consists of the regis- Working Register Group 0 in ERF Bank F consists of the control ters for Z8 General-Purpose Registers and ports. Table 2-6 registers for STOP mode, WDT, and port control. Table 2-7 shows the registers within this group.
Page 30: Program Memory
At addresses outside the internal ROM, the Z8 executes external The ROM Protect option is mask-programmable, to be selected program memory fetches through Port 0 and Port 1 in Ad- by the customer when the ROM code is submitted.
Page 31: Z8 External Memory
2.6 Z8 EXTERNAL MEMORY 2.6.1 External Data Memory (/DM) The Z8, in some cases, can address up to 60 Kbytes of external The Z8, in some cases, has the capability to access external pro- data memory beginning at location 4096. External Data Memory gram memory with the 16-bit Program Counter.
Page 32: Z8 Stacks
POP operation. The stack address always 0–1 Mode register (F8H) selects the stack location. Only the points to the data stored on the top of the stack. The Z8 stack is General-Purpose Registers can be used for the stack when the in- a return stack for CALL instructions and interrupts, as well as a ternal stack is selected.
Page 33: Chapter 3. Clock
3.1.1 Frequency Control Internal Clock XTAL2 In some cases, the Z8 has an EPROM/OTP option or a Mask ROM option bit to bypass the divide-by-two flip flop in Figure Buffer 3-1. This feature is used in conjunction with the low EMI option.
Page 34: External Clock Divide-By-Two (D1)
(SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). In some cases, the Z8 MCU offers software control of the oscil- lator to select low EMI drive or standard drive. The selection is 3.2.2 External Clock Divide-By-Two (D1) done by programming bit D7 of the Port Configuration (PCON) This bit can eliminate the oscillator divide-by-two circuitry.
Page 35: Oscillator Operation
The ground side of the oscillator lead caps amplifier. As the oscillator starts up, the signal amplitude grows should be connected to a single trace to the Z8 V (GND) pin. until clipping occurs, at which point the loop gain is effectively It should not be shared with any other system ground trace or reduced to unity and constant oscillation is achieved.
Page 36: Circuit Board Design Rules
• To prevent induced noise the crystal and load capacitors should be greater than 10 Mohms. should be physically located as close to the Z8® as possible. • Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry and the internal system clock output should be separated as much as possible.
Page 37: Crystals And Resonators
This trace should not be shared with any other compo- nents except at the V pin of the Z8. In some cases, the Z8 XTAL1 pin also functions as one of the EPROM high-voltage mode programming pins or as a special Figure 3-7. Crystal/Ceramic Resonator Oscillator factory test pin.
Page 38: Lc Oscillator
= 55.2 pf and C = 55.2 pf. 3.6 RC OSCILLATOR In some cases, the Z8 has a RC oscillator option. Please refer to the specific product specification for availability. The RC oscil- lator requires a resistor across XTAL1 and XTAL2. An addition-...
Page 39: Reset
A system reset overrides all other operating conditions and puts DS is forced Low, and R//W remains High. The program counter the Z8 into a known state. To initialize the chip’s internal logic, is loaded with 000CH. I/O ports and control registers are config- the RESET input must be held Low for at least 21 SCP or 5 ured to their default reset state.
Page 40 After a reset, the first routine executed should be one that initial- The RESET pin is the input of a Schmitt-triggered circuit. Reset- izes the control registers to the required system configuration. ting the Z8 will initialize port and control registers to their de- UM001601-0803...
Page 41 RESET to function. It requires 4 internal output time is specified as T . Please refer to specific product system clocks after reset is detected for the Z8 to reset the inter- specifications for actual values. nal circuitry. An internal pull-up, combined with an external ca- pacitor of 1 uf, provides enough time to properly reset the Z8 (Figure 4-2).
Page 42 Z8 Microcontrollers Reset—Watch-Dog Timer ZiLOG 4.2 RESET PIN, INTERNAL POR OPERATION (Continued) Table 4-3. Sample Expanded Register File Bank C Reset Values Register Register Bits (HEX) Name 0 Comments SPI Compare (SCOMP) Receive Buffer U U U U U U U U...
Page 43 Select (WDTMR) XTAL 256 TpC 1024 4096 WDT/POR Counter Chain OSC. 2.6V Operating Voltage Det. 2.6V REF /WDT From Stop Mode Recovery Source Stop Delay Select (SMR) Figure 4-3. Example of Z8 Reset with RESET Pin, WDT, SMR, and POR UM001601-0803...
Page 44 CLK Source Select (WDTMR) XTAL 5ms POR 15ms 25ms 100ms WDT/POR Counter Chain Internal RC OSC. 2V Operating Voltage Det. From Stop Mode Recovery Source Stop Delay Select (SMR) Figure 4-4. Example of Z8 Reset with WDT, SMR, and POR UM001601-0803...
Page 45: Watch-Dog Timer (Wdt)
Reset—Watch-Dog Timer 4.3 WATCH-DOG TIMER (WDT) The WDT is a retriggerable one-shot timer that resets the Z8 if it The WDTMR is located in Expanded Register File Bank F, reg- reaches its terminal count. When operating in the RUN or HALT ister 0FH.
Page 46: Power-On-Reset (Por)
STOP-Mode Recovery (if bit 5 of SMR=1). POR (cold start) will always reset the Z8 control and port regis- ters to their default condition. If a Z8 has a SMR register, the WDT timeout. warm start bit will be reset to a 0 to indicate POR.
Page 47: Chapter 5. I/O Ports
I/O P ORTS 5.1 I/O PORTS The Z8 has up to 32 lines dedicated to input and output. These to provide timing, serial and parallel input/output, or comparator lines are grouped into four 8-bit ports known as Port 0, Port 1, input/output.
Page 48: Port 0
Z8 Microcontrollers I/O Ports ZiLOG 5.2 PORT 0 This section deals with only the I/O operation of Port 0. The this manual. Figure 5-2 shows a block diagram of Port 0. This di- port's external memory interface operation is covered later in agram also applies to Ports 1 and 2.
Page 49: General I/O Mode
OTP program option, or as a I/O port. These eight I/O lines can be configured under software ROM mask option. In some, the Z8 has Auto Latches hardwired control as a nibble I/O port (P03-P00 input/output and P07-P04 to the inputs.
Page 50: Read/Write Operations
Z8 Microcontrollers I/O Ports ZiLOG 5.2 PORT 0 (Continued) TTL Level Shifter Figure 5-4. Port 0 Configuration with TTL Level Shifter 5.2.2 Read/Write Operations The Port 0–1 Mode resister bits D and D are used to con- figure Port 0 nibbles. The lower nibble (P0 –P0...
Page 51: Port 1
Z8 Microcontrollers ZiLOG I/O Ports 5.3 PORT 1 Register F8H (P01M) This section deals only with the I/0 operation. The port's external Port 0-1 Mode Register (P01M) memory interface operation is discussed later in this manual. (Write-Only) Figure 5-2 shows a block diagram of Port 1.
Page 52 Z8 Microcontrollers I/O Ports ZiLOG 5.3 PORT 1 (Continued) Port 1 (I/O or AD7 - AD0) Handshake Controls /DAV1 and RDY1 (P33 and P34) OPEN-DRAIN 2.3V Hysteresis Auto Latch R ≈ 500 KΩ Figure 5-7. Port 1 Configuration with Open-Drain Capability, Auto Latch, and Schmitt-Trigger...
Page 53 Z8 Microcontrollers ZiLOG I/O Ports Port 1 (I/O or AD7 - AD0) Handshake Controls DAV1 and RDY1 (P33 and P34) TTL Level Shifter Figure 5-8. Port 1 Configuration with TTL Level Shifter UM001601-0803...
Page 54: Read/Write Operations
Z8 Microcontrollers I/O Ports ZiLOG 5.3.2 Read/Write Operations 5.3.3 Handshake Operations In byte input or byte output mode, the port is accessed as Gener- When used as an I/O port, Port 1 can be placed under handshake al-Purpose Register P1 (01H). The port is written by specifying...
Page 55 Z8 Microcontrollers ZiLOG I/O Ports 5.4 PORT 2 Port 2 is a general-purpose port. Figure 5-2 shows a block dia- Register F6H gram of Port 2. Each of its lines can be independently pro- Port 2 Mode Register (P2M) grammed as input or output via the Port 2 Mode Register (F6H) (Write-Only) as seen in Figure 5-11.
Page 56: Port 2
Z8 Microcontrollers I/O Ports ZiLOG 5.4 PORT 2 (Continued) Open-Drain TTL Level Shifter Figure 5-13. Port 2 Configuration with TTL Level Shifter 5-10 UM001601-0803...
Page 57 Z8 Microcontrollers ZiLOG I/O Ports OPEN-DRAIN P20 OE SPI EN P20 OUT P20 IN SPI DI Auto Latch R ≈ 500 KΩ OPEN-DRAIN Standard P27 OUT SPI DO SPI DO Standard P27 OE SPI Active SCON 0 SOI D0 Enable...
Page 58: Handshake Operation
Z8 Microcontrollers I/O Ports ZiLOG 5.4.2 Read/Write Operations pin is returned. Under normal loading conditions, this is equiva- lent to reading the output register. However, if a bit of Port 2 is Port 2 is accessed as General-Purpose Register P2 (02H). Port 2 defined as an open-drain output, the data returned is the value is written by specifying P2 as an instruction’s destination regis-...
Page 59 5.5.1 General Port I/O The inputs can be Schmitt-triggered, level-shifted, or single-trip point buffered. In some cases, the Z8 may have auto latches Port 3 differs structurally from Port 0, 1, and 2. Port 3 lines are hardwired on certain Port 3 inputs and Low-EMI capabilities on fixed as four inputs (P33–P30) and four outputs (P37–P34) Port...
Page 60: Port 3
Z8 Microcontrollers I/O Ports ZiLOG 5.5 PORT 3 (Continued) Port 3 (I/O or Control) Auto Latch R ≈ 500 KΩ P30 Data Latch IRQ3 R247 = P3M 1 = Analog 0 = Digital DIG. P31 (AN1) IRQ2, T , P31 Data Latch...
Page 61 Z8 Microcontrollers ZiLOG I/O Ports P37 OUT REF (P33) P37 OUT REF (P33) PCON 0 P34, P37 Standard Output 1 P34, P37 Comparator Output Figure 5-19. Port 3 Configuration with Comparator UM001601-0803 5-15...
Page 62 Z8 Microcontrollers I/O Ports ZiLOG 5.5 PORT 3 (Continued) SK IN SPI EN SPI MSTR SPI EN SK OUT P34 OUT SPI EN SPI MSTR P34 OUT PCON 0 P34, P35 Standard Output 1 P34, P35 Comparator Output Figure 5-20. Port 3 Configuration with SPI and Comparator Outputs Using P34 and P35...
Page 63: Read/Write Operations
Z8 Microcontrollers ZiLOG I/O Ports Port 3 Output Configuration TTL Level Shifter Port 3 Input Configuration Auto Latch R ≈ 500 KΩ Figure 5-21. Port 3 Configuration with TTL Level Shifter and Auto Latch 5.5.2 Read/Write Operations 5.5.3 Special Functions Port 3 is accessed as a General-Purpose Register P3 (03H).
Page 64 Z8 Microcontrollers I/O Ports ZiLOG Register F7H Port 3 Mode Register (Write-Only) D7 D6 D5 D4 D3 D2 D1 D0 0 Port 2 Open-Drain 1 Port 2 Push-Pull 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode 0 P32 = Input...
Page 65: Port Handshake
The I/O device returns the line High in response to RDY going Low. The Z8 RR software must respond to the interrupt request and read the contents of the port in order for the State 5. handshake sequence to be completed. The RDY line goes High if and only if the port has been read and is High.
Page 66 Valid Data State 1. RDY input is High indicating that the I/O device is ready to accept data. The Z8 Writes to the port register to initiate a data transfer. Writing to the port outputs new data and State 2. forces Low if and only if RDY is High.
Page 67 In applications requiring a strobed signal instead of the inter- • In the Strobed Output Mode, the RDY input should be tied to locked handshake, the Z8 MCU can satisfy this requirement as the DAV output. follows: Figures 5-25 and 5-26 illustrate the strobed handshake connec- •...
Page 68: I/O Port Reset Conditions
5.7.1 Full Reset After a hardware reset, Watch-Dog Timer (WDT) reset, or a Z8 has the P01M, P2M, and P3M control register set back to the Power-On Reset (POR), Port Mode Registers P01M, P2M, and default condition after reset while others do not.
Page 69 Z8 Microcontrollers ZiLOG I/O Ports Register F6H Port 2 Mode Register (P2M) (Write-Only) Port 2 Mode 0 = Output 1 = Input Figure 5-28. Port 2 Reset Register F7H Port 3 Mode Register (P3M) (Write-Only) 0 0 0 0 Port 2 Open-Drain...
Page 70: Analog Comparators
5.8.1 Comparator Description Two on-board comparators can process analog signals on P31 Select Z8 devices include two independent on-chip analog com- and P32 with reference to the voltage on P33. The analog func- parators. See the device product specification for feature avail- tion is enabled by programming the Port 3 Mode Register (P3M ability and use.
Page 71 Z8 Microcontrollers I/O Ports ZiLOG 5.8 ANALOG COMPARATORS (Continued) Port 3 (I/O or Control) Auto Latch R ≈ 500 KΩ P30 Data Latch IRQ3 R247 = P3M 1 = Analog 0 = Digital DIG. P31 (AN1) IRQ2, T , P31 Data Latch...
Page 72: Comparator Programming
Z8 Microcontrollers I/O Ports ZiLOG P34 OUT REF (P33) P37 OUT REF (P33) PCON 0 P34, P37 Standard Output 1 P34, P37 Comparator Output Figure 5-33. Port 3 Configuration 5.8.2 Comparator Programming Example of enabling analog comparator output. Example of enabling analog comparator mode.
Page 73: Comparator Operation
Z8 Microcontrollers ZiLOG I/O Ports 5.8.3 COMPARATOR OPERATION 5.8.5.2 V OFFSET The absolute value of the voltage between the positive input and After enabling the Analog Comparator mode, P33 becomes a the reference input required to make the comparator output volt- common reference input for both comparators.
Page 74: Open-Drain Configuration
Figure 5-34. Port 2 Configuration offer a ROM Mask or OTP programming option to configure the Z8 Ports and oscillator globally to a Low-EMI mode (where the Other Z8s that have a Port Configuration Register (PCON) that XTAL frequency is set equal to the internal system clock fre- can configure Port 0 and Port 1 to provide open-drain outputs.
Page 75: Input Protection
Z8 Microcontrollers ZiLOG I/O Ports For Z8s having the PCON register feature, the following bits • Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=0) or configured as a control the Low EMI options: Standard Port by setting this bit (D6=1).
Page 76 A simplified schematic of the open circuit conditions using Auto Latches. An Auto Latch is a CMOS Z8 I/O circuit is shown in Figure 5-38. circuit which, in the event of an open circuit condition, latches the input at a valid CMOS level.
Page 77 Rext. In summary, the CMOS Z8 Auto Latch inhibits excessive cur- rent drain in Z8 devices by latching an open input to either V or GND. The effect of the Auto Latch on the I/O characteristics UM001601-0803...
Page 78 Z8 Microcontrollers I/O Ports ZiLOG 5-32 UM001601-0803...
Page 79: Introduction
OUNTER IMERS 6.1 INTRODUCTION ® The Z8 MCU provides up to two 8-bit counter/timers, T0 and Each counter/timer operates in either Single-Pass or Continuous T1, each driven by its own 6-bit prescaler, PRE0 and PRE1 (Fig- mode. At the end-of-count, counting either stops or the initial ure 6-1).
Page 80: Prescalers And Counter/Timers
Z8 Microcontrollers Counter/Timers ZiLOG Counter/timers 0 and 1 are driven by a timer clock generated by dividing the internal clock by four. The divide-by-four stage, the R245 PRE0 6-bit prescaler, and the 8-bit counter/timer form a synchronous Prescaler 0 Register (%F5;...
Page 81: Counter/Timer Operation
Z8 Microcontrollers ZiLOG Counter/Timers 6.3 COUNTER/TIMER OPERATION Under software control, counter/timers are started and stopped The counter timers remain at rest as long as the Enable Count via the Timer Mode Register (TMR,F1H) bits D (Figure 6- bits are 0. To enable counting, the Enable Count bit (D for T0 6).
Page 82: Prescaler Operations
The internal clock frequency defaults to the external clock the count sequence is: source (XTAL, ceramic resonator, and others) divided by 2. Some Z8 microcontrollers allow this divisor to be changed via 3–2–1–3–2–1–3–2–1–3... the Stop-Mode Recovery register. See the product data sheet for available clock divisor options.
Page 83: Tout Modes
Z8 Microcontrollers ZiLOG Counter/Timers 6.4 T MODES The Timer Mode Register TMR (F1H) (Figure 6-9), is used in by setting P3M bit 5 to 0. Output is controlled by one of the conjunction with the Port 3 Mode Register P3M (F7H) (Figure counter/timers (T0 or T1) or the internal clock.
Page 84 , P36 cannot be modified by a write • Configures T0 to drive the T pin (P36). ® to port register P3. However, the Z8 software can examine the P36 current output by reading the port register. • Sets the P36 T pin to a logic 1 level.
Page 85: Tin Modes
Z8 Microcontrollers ZiLOG Counter/Timers 6.5 T MODES The Timer Mode Register TMR (F1H) (Figure 6-13) is used in The counter/timer clock source must be configured for external conjunction with the Prescaler Register PRE1 (F3H) (Figure 6- by setting the PRE1 Register bit 2 to 1. The Timer Mode Regis-...
Page 86: External Clock Input Mode
Z8 Microcontrollers Counter/Timers ZiLOG It is suggested that P31 be configured as an input line by setting Each High-to-Low transition on T generates an interrupt re- P3M Register bit 5 to 0, although T is still functional if P31 is...
Page 87: Gated Internal Clock Mode
Z8 Microcontrollers ZiLOG Counter/Timers 6.5.2 Gated Internal Clock Mode The T Gated Internal Clock Mode (TMR bit 5 and bit 4 set to is Low. Interrupt request IRQ2 is generated on the High-to- 0 and 1 respectively) measures the duration of an external event.
Page 88: Triggered Input Mode
Z8 Microcontrollers Counter/Timers ZiLOG 6.5.3 Triggered Input Mode The T Triggered Input Mode (TMR bits 5 and 4 are set to 1 and T1 until software sets the Enable Count bit again. In Continuous 0, respectively) causes T1 to start counting as the result of an ex- mode, once T1 is triggered counting continues until software re- ternal event (Figure 6-17).
Page 89: Retriggerable Input Mode
Z8 Microcontrollers ZiLOG Counter/Timers 6.5.4 Retriggerable Input Mode The T Retriggerable Input Mode (TMR bits 5 and 4 are set to Subsequent T transitions will not cause T1 to load and start 1) causes T1 to load and start counting on every occurrence of a counting until software sets the Enable Count bit again.
Page 90: Reset Conditions
Z8 Microcontrollers Counter/Timers ZiLOG 6.7 RESET CONDITIONS After a hardware reset, the counter/timers are disabled and the R245 PRE0 contents of the counter/timer and prescaler registers are unde- Prescaler 0 Register fined. However, the counting modes are configured for Single- (%F5;...
Page 91: Introduction
Interrupt Mask and Interrupt Priority logic. bally disabled by resetting the master Interrupt Enable, bit 7 in The Z8 MCU family supports both vectored and polled interrupt the Interrupt Mask Register, with a Disable Interrupt (DI) in- handling.
Page 92: Interrupt Sources
Z8 Microcontrollers Interrupts ZiLOG 7.2 INTERRUPT SOURCES Table 7-1 presents the interrupt types, sources, and vectors available in the Z8 family of processors. Table 7-1. Interrupt Types, Sources, and Vectors * Name Sources Vector Location Comments , IRQ , Comparator External (P3 ), Edge Triggered;...
Page 93: Internal Interrupt Sources
Otherwise, its source is internal. The external re- IH). quest is generated by a Low edge signal on P30 as shown in Fig- ure 7-4. Again, the external request is synchronized and delayed before reaching IRQ3. Some Z8 products replace P30 with P32 (IRQ Serial In) Clock...
Page 94: Interrupt Request (Irq) Register Logic And Timing
Z8 Microcontrollers Interrupts ZiLOG 7.3 INTERRUPT REQUEST REGISTER LOGIC AND TIMING Figure 7-5 shows the logic diagram for the Interrupt Request At sample time the request is transferred to the second flip-flop (IRQ) Register. The leading edge of the request will set the first in Figure 7-5, that drives the interrupt mask and priority logic.
Page 95: Interrupt Initialization
Z8 Microcontrollers ZiLOG Interrupts 7.4 INTERRUPT INITIALIZATION After reset, all interrupts are disabled and must be initialized be- six interrupt levels IRQ0-IRQ5 are divided into three groups of fore vectored or polled interrupt processing can begin. The Inter- two interrupt requests each. One group contains IRQ3 and IRQ5.
Page 96: Interrupt Mask Register (Imr) Initialization
Z8 Microcontrollers Interrupts ZiLOG 7.4 INTERRUPT INITIALIZATION (Continued) 7.4.2 Interrupt Mask Register (IMR) Initialization IMR individually or globally enables or disables the six interrupt Note: Bit 7 must be reset by the DI instruction before the requests (Figure 7-8). When bit 0 to bit 5 are set to 1, the corre- contents of the Interrupt Mask Register or the Interrupt Priority sponding interrupt requests are enabled.
Page 97: Interrupt Request (Irq) Register Initialization
Z8 Microcontrollers ZiLOG Interrupts 7.4.3 Interrupt Request (IRQ) Register Initialization IRQ (Figure 7-9) is a read/write register that stores the interrupt For polled processing, IRQ must still be initialized by an EI in- requests for both vectored and polled interrupts. When an inter- struction.
Page 98 Z8 Microcontrollers Interrupts ZiLOG 7.4 INTERRUPT INITIALIZATION (Continued) IMR is cleared before the IRQ enabling sequence to insure no The proper sequence for programming the interrupt edge select unexpected interrupts occur when EI is executed. This code se- bits is (assumes IPR and IMR have been previously initialized): quence should be executed prior to programming the application ;Inhibit all interrupts...
Page 99: Irq Software Interrupt Generation
IRQ5 vector. ORIRQ, #NUMBER 7.6 VECTORED PROCESSING Each Z8 interrupt level has its own vector. When an interrupt oc- • Fetch High Byte of Vector curs, control passes to the service routine pointed to by the inter- •...
Page 100 Z8 Microcontrollers Interrupts ZiLOG 7.6 VECTORED PROCESSING (Continued) Program Memory XXFFH Interrupt Service Routine PC HIGH Byte FLAGS 000CH Vector Selected By Priority Logic Interrupt Vector Table 0000H Figure 7-12. Interrupt Vectoring 7-10 UM001601-0803...
Page 101: Vectored Interrupt Cycle Timing
Odd Vector Address A0-A7 OUT PC+1 SP-1 SP-3 FLAGS SP-2 VECT VECT+1 Even Vector Address Op Code (Discarded) A0-A7 IN VECTL VECTH First Instruction Of Interrupt Service Routine For Stack External Only Figure 7-13. Z8 Interrupt Acknowledge Timing UM001601-0803 7-11...
Page 102: Nesting Of Vectored Interrupts
Z8 Microcontrollers Interrupts ZiLOG 7.6.2 Nesting of Vectored Interrupts Nesting of vectored interrupts allows higher priority requests to • Proceed with interrupt processing. interrupt a lower priority request. To initiate vectored interrupt • After processing is complete, execute DI instruction.
Page 103: Introduction
HAPTER OWER ODES 8.1 INTRODUCTION ® In addition to the standard RUN mode, the Z8 MCU supports two Power-Down modes to minimize device current consump- tion. The two modes supported are HALT and STOP. 8.2 HALT MODE OPERATION The HALT mode suspends instruction execution and turns off The HALT mode may also be exited via a POR/RESET activa- the internal CPU clock.
Page 104: Stop Mode Operation
• is at the low end of the devices operating range. Some Z8 devices allow for the on-chip WDT to run in the STOP • WDT is off in the STOP mode.
Page 105: Stop-Mode Recovery Register (Smr)
Figure 8-1. STOP-Mode Recovery Register (Write-Only Except Bit D7, Which Is Read-Only) Note: The SMR register is available in select Z8 MCU products. Refer to the device product specification to determine SMR options available. SCLK/TCLK Divide-by-16 Select (DO). This bit of the SMR External Clock Divide-by-Two (D1).
Page 106 POR and/or external reset recovery wakes the Z8 from STOP mode. A 0 indicates low-level recov- P30 transition ery. The default is 0 on POR (Figure 8-2).
Page 107: Chapter 9. Serial I/O
HAPTER ERIAL 9.1 UART INTRODUCTION ® Select Z8 MCU microcontrollers contain an on-board full-du- Counter/Timer T0 and Port 3 I/O lines P30 (input) and P37 (out- plex Universal Asynchronous Receiver/Transmitter (UART) for put). Counter/Timer T0 provides the clock input for control of data communications.
Page 108: Uart Bit-Rate Generation
T0 Prescaler PRE0 The SIO Register and its associated Mode Control Registers are Timer/Counter0 mapped into the Standard Z8 Register File as shown in Table 9- Timer Mode 1. The organization allows the software to access the UART as UART general-purpose registers, eliminating the need for special in- structions.
Page 109 Z8 Microcontrollers ZiLOG Serial I/O For example, given an input clock frequency (XTAL) of Table 9-2 lists several commonly used bit rates and the values of 11.9808 MHz and a selected bit rate of 1200 bits per second, the XTAL, p, and t required to derive them. This list is presented for equation is satisfied by p = 39 and t = 2.
Page 110: Uart Receiver Operation
Z8 Microcontrollers Serial I/O ZiLOG The bit rate generator is started by setting the Timer Mode Reg- Counter/Timer0 Register to their corresponding down counters. ister (TMR) (F1H) bit 1 and bit 0 both to 1 (Figure 9-5). This In addition, counting is enabled so that UART operations begin.
Page 111: Overwrites
If parity is on, bit 7 of (IRQ3). The Z8 does not have a flag to indicate this overrun con- the data received will be replaced by a Parity Error Flag. A parity dition.
Page 112: Transmitter Operation
Z8 Microcontrollers Serial I/O ZiLOG 9.4 TRANSMITTER OPERATION 9.4.1 Overwrites The transmitter consists of a transmitter buffer (SIO Register [F0H]), a parity generator, and associated control logic. The The user is not protected from overwriting the transmitter, so it transmitter block diagram is shown as part of Figure 9-1.
Page 113: Uart Reset Conditions
Z8 Microcontrollers ZiLOG Serial I/O 9.5 UART RESET CONDITIONS After a hardware reset, the SIO Register contents are undefined, show the binary reset values of the SIO Register and its associ- and Serial Mode and parity are disabled. Figures 9-10 and 9-11 ated mode register P3M.
Page 114: Serial Peripheral Interface (Spi)
ZiLOG 9.6 SERIAL PERIPHERAL INTERFACE (SPI) SCON (C) 02 Select Z8 microcontrollers incorporate a serial peripheral inter- D7 D6 D5 D4 D3 D2 D1 D0 face (SPI) for communication with other microcontrollers and peripherals. The SPI includes features such as Stop-Mode Re- SPI Enable covery, Master/Slave selection, and Compare mode.
Page 115: Spi Operation
Z8 Microcontrollers ZiLOG Serial I/O 9.7 SPI OPERATION 9.8 SPI COMPARE The SPI is used in one of two modes: either as system slave, or When the SPI Compare Enable bit, D3 of the SCON Register is as system master. Several of the possible system configurations set to 1, the SPI Compare feature is enabled.
Page 116 Z8 Microcontrollers Serial I/O ZiLOG Standard Serial Setup Master ss sk do di ss sk do di ss sk do di ss sk do di Slave Slave Slave Slave Standard Parallel Setup Master ss sk do di ss sk do di...
Page 117: Receive Character Available And Overrun
Z8 Microcontrollers ZiLOG Serial I/O 9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN When a complete data stream is received, an interrupt is gener- trol Register is used to log any RxCharOverrun (Figure 9-14 and ated and the RxCharAvail bit in the SCON Register is set. Bit 4 Figure 9-15).
Page 118 Z8 Microcontrollers Serial I/O ZiLOG 9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN (Continued) Port Control SPI Compare Register (SCOMP) Bit Control /Interrupt Control SPI Shift Register SPI Receive Buffer (RxBUF) SPI Control Clock TCLK SCLK + n Figure 9-15. SPI Logic...
Page 119 Z8 Microcontrollers ZiLOG Serial I/O OPEN-DRAIN P20 OE SPI EN P20 IN SPI DI Auto Latch R ≈ 500 KΩ OPEN-DRAIN Standard P27 OUT SPI DO SPI DO Standard P27 OE SPI Active SCON 0 SOI D0 Enable 1 P27 OUT...
Page 120 Z8 Microcontrollers Serial I/O ZiLOG 9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN (Continued) SK IN SPI EN SPI MSTR SPI EN SK OUT P34 OUT SPI EN SPI MSTR P35 OUT PCON 0 P34, P35 Standard Output 1 P34, P35 Comparator Output Figure 9-17.
Page 121 Z8 Microcontrollers ZiLOG Serial I/O UM001601-0803 9-15...
Page 122 Z8 Microcontrollers Serial I/O ZiLOG 9-16 UM001601-0803...
Page 123: Introduction
XTERNAL NTERFACE 10.1 INTRODUCTION The Z8 can be a microcontroller with 20 pins for external mem- The Z8 has a multiplexed external memory interface. In the mul- ory interfacing. The external memory interface on the Z8 is gen- tiplexed mode, eight pins from Port 1 form an Address/Data Bus erally for either RAM or ROM.
Page 124: Pin Descriptions
Memory (DM) signals are valid for program or data memory 10.2.6 P17 - P10 transfers. In some cases, the Z8 address strobe is pulsed low re- Address/Data Lines AD7 - AD0 (inputs/outputs, TTL-compati- gardless of accessing external or internal memory. Please refer ble).
Page 125: External Addressing Configuration
Z8 Microcontrollers ZiLOG External Interface 10.3 EXTERNAL ADDRESSING CONFIGURATION The minimum bus configuration uses Port 1 as a multiplexed ad- Port 0 can be programmed to provide either four additional ad- dress/data port (AD7 - AD0), allowing access to 256 bytes of ex- dress lines (A11- A8), which increases the addressable memory ternal memory.
Page 126: External Stacks
Figure 10-3. Z8 Stack Selection 10.5 DATA MEMORY The two Z8 external memory spaces, data and program, are ad- and High for the execution of program instructions. DM is also dressed as two separate spaces of up to 64 Kbytes each. External...
Page 127: Bus Operation
12 clock periods depending on the operation be- signals. ing performed. The notations used to describe the basic timing periods of the Z8 are machine cycles (Mn), timing states (Tn), and clock periods. All timing references are made with respect Machine Cycle...
Page 128: Address Strobe
10.6.2 Data Strobe (/DS) All transactions start with AS driven Low and then raised High The Z8 uses DS to time the actual data transfer. For Write oper- by the Z8 MCU. The rising edge of AS indicates that R/W, DM ations (R/W = Low), a Low on DS indicates that valid data is on (if used), and the address outputs are valid.
Page 129: Extended Bus Timing
Z8 Microcontrollers ZiLOG External Interface 10.7 EXTENDED BUS TIMING Some products can accommodate slow memory access time by Figures 10-7 and 10-8 illustrate extended external memory Read automatically inserting an additional software controlled state and Write cycles. time (Tx). This stretches the DS timing by two clock periods.
Page 130 Z8 Microcontrollers External Interface ZiLOG Machine Cycle Clock A15-A8 A15-A8 AD7-AD0 A7-A0 D7-D0 OUT Write Cycle Figure 10-8. Extended External Memory Write Cycle Timing is extended by setting bit D5 in the Port 0-1 Mode Reg- Register F8H (P01M) ister (F8H) to 1 (Figure 10-9). After a RESET, this bit is set to 0.
Page 131: Instruction Timing
ZiLOG External Interface 10.8 INSTRUCTION TIMING The High throughput of the Z8 is due, in part, to the use of an require execution time longer than that of the overlapped fetch, instruction pipeline, in which the instruction fetch and execution or reference program or data memory as part of their execution, cycles are overlapped.
Page 132: Z8 Reset Conditions
Figure 10-11. Instruction Cycle Timing (2- and 3-Byte Instructions) 10.9 Z8 RESET CONDITIONS After a hardware reset, extended timing is set to accommodate slow memory access during the configuration routine, DM is in- active, the stack resides in the register file.
Page 133: Introduction
Direct (D) or 4, 6,..238 for actual registers. • Relative (RA) In the following definitions of Z8 Addressing Modes, the use of'register' can also imply register pair, working register, or • Immediate (IM) working register pair, depending on the context.
Page 134: Z8 Register Addressing (R)
Z8 Microcontrollers Addressing Modes ZiLOG 11.2 Z8 REGISTER ADDRESSING (R) In 8-bit Register Addressing mode, the operand value is equiva- In the Register Addressing (Figure 11-1), the destination and/or lent to the contents of the specified register or register pair.
Page 135: Z8 Indirect Register Addressing (Ir)
Z8 Microcontrollers ZiLOG Addressing Modes 11.3 Z8 INDIRECT REGISTER ADDRESSING (IR) In the Indirect Register Addressing Mode, the contents of the When accessing program memory or External Data Memory, specified register are equivalent to the address of the operand register pairs or Working Register pairs are used to hold the 16- (Figures 11-3 and 11-4).
Page 136 Z8 Microcontrollers Addressing Modes ZiLOG 11.3 Z8 INDIRECT REGISTER ADDRESSING (IR) (Continued) Register File Points to Origin Program Memory of Working Register Group Register Pair LSB Register 4-Bit Working Pair MSB Registers Address Points to Working Register Instruction Example Pair (Even...
Page 137: Z8 Indexed Addressing (X)
Z8 Microcontrollers ZiLOG Addressing Modes 11.4 Z8 INDEXED ADDRESSING (X) The Indexed Addressing Mode is used only by the Load (LD) in- of the operand. Figure 11-5 illustrates this addressing conven- struction. An indexed address consists of a register address off- tion.
Page 138: Z8 Direct Addressing (Da)
Z8 Microcontrollers Addressing Modes ZiLOG 11.5 Z8 DIRECT ADDRESSING (DA) The Direct Addressing mode, as shown in Figure 11-6, specifies ditional Jump (JP) and Call (CALL) instructions use this ad- the address of the next instruction to be executed. Only the Con- dressing mode.
Page 139: Z8 Relative Addressing (Ra)
Z8 Microcontrollers ZiLOG Addressing Modes 11.6 Z8 RELATIVE ADDRESSING (RA) In the Relative Addressing mode, illustrated in Figure 11-7, the tion following the Jump Relative (JR) or Decrement and Jump if instruction specifies a two’s-complement signed displacement in Non-Zero (DJNZ) instruction. JR and DJNZ are the only instruc- the range of –128 to +127.
Page 140: Z8 Immediate Data Addressing (Im)
Z8 Microcontrollers Addressing Modes ZiLOG 11.7 Z8 IMMEDIATE DATA ADDRESSING (IM) Immediate data is considered an “addressing mode” for the pur- of the instruction, it is always located in the Program Memory poses of this discussion. It is the only addressing mode that does address space (Figure 11-8).
Page 141: Z8 Functional Summary
’ ANUAL HAPTER NSTRUCTION 12.1 Z8 FUNCTIONAL SUMMARY Z8 instructions can be divided functionally into the following Table 12-2. Arithmetic Instructions eight groups: Mnemonic Operands Instruction • Load dst, src Add with Carry • Bit Manipulation dst, src dst, src Compare •...
Page 142: Processor Flags
12.2 PROCESSOR FLAGS The Flag Register (FCH) informs the user of the current status of the Z8. The flags and their bit positions in the Flag Register are shown in Figure 12-1. The Z8 Flag Register contains six bits of status information which are set or cleared by CPU operations.
Page 143 D7 D6 D5 D4 D3 D2 D1 D0 User Flag (F1) User Flag (F2) Half Carry Flag (H) Decimal Adjust Flag (D) Overflow Flag (V) Sign Flag (S) Zero Flag (Z) Carry Flag (C) Figure 12-1. Z8 Flag Register UM001601-0803 12-3...
Page 144 Z8 Microcontrollers Instruction Set ZiLOG 12.2.1 Carry Flag (C) and subtraction, this flag specifies what type of instruction was last executed so that the subsequent Decimal Adjust (DA) oper- The Carry Flag is set to 1 whenever the result of an arithmetic ation can function properly.
Page 145: Condition Codes
9, 12-10, and 12-11. Notation for the flags and how they are af- flag settings are encoded in a 4-bit field called the condition code fected are as follows: (cc), which forms bits 4-7 of the conditional instructions. Table 12-9. Z8 Flag Definitions Table 12-10. Flag Settings Definitions Flag Description...
Page 146 Z8 Microcontrollers Instruction Set ZiLOG 12.4 NOTATION AND BINARY ENCODING In the detailed instruction descriptions that make up the rest of tional shorthand. Operands, condition codes, address modes, and this chapter, operands and status flags are represented by a nota- their notations are as follows (Table 12-12): Table 12-12.
Page 147 Z8 Microcontrollers ZiLOG Instruction Set 12.4.1 Assembly Language Syntax Additional symbols used are: For proper instruction execution, Z8 assembly language syntax Table 12-13. Additional Symbols requires ‘dst, src’ be specified, in that order. The following in- Symbol Definition struction descriptions show the format of the object code pro- duced by the assembler.
Page 148: Z8 Instruction Summary
Z8 Microcontrollers Instruction Set ZiLOG 12.5 Z8 INSTRUCTION SUMMARY Address IRET Instruction Op Code Mode Flags Affected FLAGS←@SP; and Operation Byte (Hex) C Z S V D H SP ← SP + 1 ADC dst, src † 1[ ] dst ← dst + src PC ←...
Page 149 Z8 Microcontrollers ZiLOG Instruction Set Address Op Code TCM dst, src † 6[ ] – 0 – – Instruction Mode Byte Flags Affected (NOT dst) AND and Operation dst (Hex) C Z S V D H POP dst – – – – – –...
Page 150 Z8 Microcontrollers Instruction Set ZiLOG 12.5.1 Op Code Map Lower Nibble (Hex) 10.5 10.5 10.5 10.5 12/10.5 12/10.0 12.10.0 DJNZ r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, R2 r2, R1 r1, RA cc, RA...
Page 151: Instruction Description And Formats
Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats 12.6 INSTRUCTION DESCRIPTION AND FORMATS ADD WITH CARRY Add With Carry ADC dst, src Instruction Format: Address Mode (Hex) Cycles Operation: dst <— dst + src + C The source operand, along with the setting of the Carry (C) Flag, is added to the destination operand. Two’s complement addition is performed.
Page 152 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG ADD WITH CARRY Example: If Working Register R16 contains 16H, the C Flag is not set, Working Register R10 contains 20H, and Register 20H contains 11H, the statement: ADC R16, @R10 Op Code: 13 FA leaves the value 27H in Working Register R16.
Page 153 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats ADD dst, src Instruction Format: Operation: dst <— dst + src The source operand is added to the destination operand. Two’s complement addition is performed. The sum is stored in the destination operand. The contents of the source operand are not affected.
Page 154 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG Example: If Working Register R16 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11H, the statement: ADD R16, @R10 Op Code: 03 FA leaves the value 27H in Working Register R16. The C, Z, S, V, D, and H Flags are all cleared.
Page 155 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats Logical AND Logical AND AND dst, src Instruction Format: Operation: dst <— dst AND src The source operand is logically ANDed with the destination operand. The AND operation results in a 1 being stored whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored.
Page 156 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG Logical AND Example: If Working Register R4 contains F9H (11111001B), Working Register R13 contains 7BH, and Register 7BH contains 6AH (01101010B), the statement: AND R4, @R13 Op Code: 53 4D leaves the value 68H (01101000B) in Working Register R4. The Z, V, and S Flags are cleared.
Page 157 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats CALL CALL PROCEDURE CALL Call Procedure CALL dst Instruction Format: Operation: SP <— SP - 2 @SP <— PC PC <— dst The Stack pointer is decremented by two, the current contents of the Program Counter (PC) (address of the first instruction following the CALL instruction) are pushed onto the top of the Stack, and the specified destination address is then loaded into the PC.
Page 158 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG CALL Call Procedure Example: If the contents of the PC are 1A47H and the contents of the SP (Registers FEH and FFH) are 3002H, the statement: CALL 3521H Op Code: D6 35 21 causes the SP to be decremented to 3000H, 1A4AH (the address following the CALL instruction) to be stored in external data memory 3000 and 3001H, and the PC to be loaded with 3521H.
Page 159 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats COMPLEMENT CARRY FLAG Complement Carry Flag Instruction Format: Operation: C <— NOT C The C Flag is complemented. If C = 1, then it is changed to C = 0; or, if C = 0, then it is changed to C = 1.
Page 160 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG CLEAR CLEAR CLR dst Instruction Format: Operation: dst <— 0 The destination operand is cleared to 00H. Flags: Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Note: Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand.
Page 161 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats COMPLEMENT Complement COM dst Instruction Format: Operation: dst <— NOT dst The contents of the destination operand are complemented (one’s complement). All 1 bits are changed to 0, and all 0 bits are changed to 1.
Page 162 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG COMPARE Compare CP dst, src Instruction Format: Operation: dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected.
Page 163 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats COMPARE Example: If Working Register R15 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11H, the statement: CP R16, @R10 Op Code: A3 FA clears the C, Z, S, and V Flags.
Page 164 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG DECIMAL ADJUST Decimal Adjust DA dst Instruction Format: Operation: dst <— DA dst The destination operand is adjusted to form two 4-bit BCD digits following a binary addition or subtraction operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the following table indicates the operation performed.
Page 165 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats Example: If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic.
Page 166 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG DECREMENT Decrement DEC dst Instruction Format: Operation: dst <— dst - 1 The contents of the destination operand are decremented by one. Flags: Unaffected Set if the result is zero; cleared otherwise Set if the result of bit 7 is set (negative); cleared otherwise Set if arithmetic overflow occurs;...
Page 167 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats DECW DECREMENT WORD DECW Decrement Word DECW dst Instruction Format: Operation: dst <— dst - 1 The contents of the destination (which must be an even address) operand are decremented by one. The destination operand can be a Register Pair or a Working Register Pair.
Page 168 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG DISABLE INTERRUPTS Disable Interrupts Instruction Format: Operation: IMR (7) <— 0 Bit 7 of Control Register FBH (the Interrupt Mask Register) is reset to 0. All interrupts are disabled, although they remain “potentially” enabled. (For instance, the Global Interrupt Enable is cleared, but not the individual interrupt level enables.)
Page 169 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats DJNZ DECREMENT AND JUMP IF NON-ZERO DJNZ Decrement and Jump if Non-zero DJNZ r, dst Instruction Format: Operation: r <— r - 1; If r <> 0, PC <— PC + dst The specified Working Register being used as a counter is decremented. If the contents of the specified Working Register are not zero after decrementing, then the relative address is added to the Program Counter (PC) and control passes to the statement whose address is now in the PC.
Page 170 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG ENABLE INTERRUPTS Enable Interrupts Instruction Format: Operation: IMR (7) <— 0 Bit 7 of Control Register FBH (the Interrupt Mask Register) is set to 1. This allows potentially enabled interrupts to become enabled.
Page 171 In order to enter HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP immediately before the execution of the HALT instruction. Example: Assuming the Z8 is in normal operation, the statements: HALT Op Codes: FF 7F place the Z8 into HALT mode.
Page 172 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG INCREMENT Increment Instruction Format: Operation: dst <— dst + 1 The contents of the destination operand are incremented by one. Flags: Unaffected Set if the result is zero; cleared otherwise. Set if the result of bit 7 is set (negative); cleared otherwise.
Page 173 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats INCW INCREMENT WORD INCW Increment Word INCW dst Instruction Format: Address Mode Cycles (Hex) Operation: dst <— dst - 1 The contents of the destination (which must be an even address) operand is decremented by one. The destination operand can be a Register Pair or a Working Register Pair.
Page 174 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG IRET INTERRUPT RETURN IRET Interrupt RETURN IRET Instruction Format: Operation: FLAGS <— @SP SP <— SP + 1 PC <— @SP SP <— SP + 2 IMR (7) <— 1 This instruction is issued at the end of an interrupt service routine. It restores the Flag Register (Control Register FCH) and the PC.
Page 175 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats JUMP JUMP JP cc, dst Instruction Format: Operation: If cc (condition code) is true, then PC <— dst A conditional jump transfers Program Control to the destination address if the condition specified by cc (condition code) is true.
Page 176 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG JUMP RELATIVE Jump Relative JR cc, dst Instruction Format: Address Mode Cycles (Hex) 12 if jump taken 10 if jump not taken cc = 0 to F Operation: If cc is true, PC <— PC + dst If the condition specified by the “cc”...
Page 177 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LOAD Load LD dst, src Instruction Format: Operation: dst <— src The contents of the source operand are loaded into the destination operand. The contents of the source operand are not affected. Flags:...
Page 178 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG LOAD Example: The statement: LD R15, #34H Op Code: FC 34 loads the value 34H into Working Register R15. Example: If Register 34H contains the value FCH, the statement: LD R14, 34H Op Code: F8 34 loads the value FCH into Working Register R15.
Page 179 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LOAD Example: If Register 45H contains the value CFH and Register CFH contains the value FFH, the statement: LD 34H, @45H Op Code: E5 45 34 loads the value FFH into Register 34H. The contents of Register 45H and Register CFH are not affected.
Page 180 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG LOAD CONSTANT Load Constant LDC dst, src Instruction Format: Address Mode Cycles (Hex) Operation: dst <— src This instruction is used to load a byte constant from program memory into a Working Register, or vice versa. The address of the program memory location is specified by a Working Register Pair.
Page 181 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LDCI LOAD CONSTANT AUTO-INCREMENT LDCI Load Constant Auto-increment LDCI dst, src Instruction Format: Address Mode Cycles (Hex) Operation: dst <— src r <— r + 1 rr <— rr + 1 This instruction is used for block transfers of data between program memory and the Register File. The address of the program memory location is specified by a Working Register Pair, and the address of the Register File location is specified by Working Register.
Page 182 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG LDCI LOAD CONSTANT AUTO-INCREMENT Example: If Working Register R2 contains 20H, Register 20H contains 22H, Register 21H contains BCH, and Working Register Pair R6-R7 contains 30A2H, the statement: LDCI @RR6, @R2 Op Code: D3 26 loads the value 22H into program memory location 30A2H.
Page 183 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LOAD EXTERNAL DATA Load External Data LDE dst, src Instruction Format: Address Mode Cycles (Hex) Operation: dst <— src This instruction is used to load a byte from external data memory into a Working Register or vice versa. The address of the external data memory location is specified by a Working Register Pair.
Page 184 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG LDEI LOAD EXTERNAL DATA AUTO-INCREMENT LDEI Load External Data Auto-increment LDEI dst, src Instruction Format: Address Mode Cycles (Hex) Operation: dst <— src r <— r + 1 rr <— rr + 1 This instruction is used for block transfers of data between external data memory and the Register File.
Page 185 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LDEI LOAD EXTERNAL DATA AUTO-INCREMENT Example: If Working Register R2 contains 22H, Register 22H contains ABH, Register 23H contains C3H, and Working Register Pair R6 and R7 contains 404AH, the statement: LDEI @RR6, @R2 Op Code: 93 26 loads the value ABH into external data memory location 404AH.
Page 186 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG NO OPERATION No Operation Instruction Format: Operation No action is performed by this instruction. It is typically used for timing delays or clearing the pipeline. Flags: Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected 12-46...
Page 187 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LOGICAL OR Logical OR OR dst, src Instruction Format: Operation: dst <— dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination operand.
Page 188 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG LOGICAL OR Example: If Working Register R4 contains F9H (11111001B), Working Register R13 contains 7BH, and Register 7B contains 6AH (01101010B), the statement: OR R4, @R13 Op Code: 43 4D leaves the value FBH (11111011B) in Working Register R4. The S Flag is set, and the Z and V Flags are cleared.
Page 189 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats POP dst Instruction Format: Operation: dst <— @SP SP <— SP + 1 The contents of the location specified by the SP (Stack Pointer) are loaded into the destination operand. The SP is then incremented automatically.
Page 190 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG PUSH PUSH PUSH Push PUSH src Instruction Format: Address Mode (Hex) Cycles 10 Internal Stack 12 External Stack 10 Internal Stack 10 External Stack Operation: SP <— SP - 1 @SP <— src The contents of the SP (stack pointer) are decremented by one, then the contents of the source operand are loaded into the location addressed by the decremented SP, thus adding a new element to the stack.
Page 191 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats RESET CARRY FLAG Reset Carry Flag Instruction Format: Operation: C <— 0 The C Flag is reset to 0, regardless of its previous value. Flags: Reset to 0 Unaffected Unaffected Unaffected Unaffected Unaffected...
Page 192 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG RETURN Return Instruction Format: Operation: PC <— @SP SP <— SP + 2 This instruction is normally used to return from a procedure entered by a CALL instruction. The contents of the location addressed by the SP are popped into the PC. The next statement executed is the one addressed by the new contents of the PC.
Page 193 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats ROTATE LEFT Rotate Left RL dst Instruction Format: Operation: C <— dst(7) dst(0) <— dst(7) dst(1) <— dst(0) dst(2) <— dst(1) dst(3) <— dst(2) dst(4) <— dst(3) dst(5) <— dst(4) dst(6) <— dst(5) dst(7) <—...
Page 194 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG ROTATE LEFT Example: If the contents of Register C6H are 88H (10001000B), the statement: RL C6H Op Code: 80 C6 leaves the value 11H (00010001B) in Register C6H. The C and V Flags are set, and the S and Z Flags are cleared.
Page 195 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats ROTATE LEFT THROUGH CARRY Rotate Left Through Carry RLC dst Instruction Format: Operation: C<— dst(7) dst(0) <— C dst(1) <— dst(0) dst(2) <— dst(1) dst(3) <— dst(2) dst(4) <— dst(3) dst(5) <— dst(4) dst(6) <—...
Page 196 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG ROTATE LEFT THROUGH CARRY Example: If the C Flag is reset and Register C6 contains 8F (10001111B), the statement: RLC C6 Op Code: 10 C6 leaves Register C6 with the value 1EH (00011110B). The C and V Flags are set, and S and Z Flags are cleared.
Page 197 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats ROTATE RIGHT Rotate Right RR dst Instruction Format: Operation: C <— dst(0) dst(0) <— dst(1) dst(1) <— dst(2) dst(2) <— dst(3) dst(3) <— dst(4) dst(4) <— dst(5) dst(5) <— dst(6) dst(6) <— dst(7) dst(7) <—...
Page 198 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG ROTATE RIGHT Example: If the contents of Working Register R6 are 31H (00110001B), the statement: RR R6 Op Code: E0 E6 leaves the value 98H (10011000) in Working Register R6. The C, V, and S Flags are set, and the Z Flag is cleared.
Page 199 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats ROTATE RIGHT THROUGH CARRY Rotate Right Through Carry RRC dst Instruction Format: Operation: C <— dst(0) dst(0) <— dst(1) dst(1) <— dst(2) dst(2) <— dst(3) dst(3) <— dst(4) dst(4) <— dst(5) dst(5) <— dst(6) dst(6) <—...
Page 200 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG ROTATE RIGHT THROUGH CARRY Example: If the contents of Register C6H are DDH (11011101B) and the C Flag is reset, the statement: RRC C6H Op Code: C0 C6 leaves the value 6EH (01101110B) in register C6H. The C and V Flags are set, and the Z and S Flags are cleared.
Page 201 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats SUBTRACT WITH CARRY Subtract With Carry SBC dst, src Instruction Format: Operation: dst <— dst - src - C The source operand, along with the setting of the C Flag, is subtracted from the destination operand and the result is stored in the destination operand.
Page 202 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG SUBTRACT WITH CARRY Example: Working Register R3 contains 16H, the C Flag is set to 1, and Working Register R11 contains 20H, the statement: SBC R3, R11 Op Code: 32 3B leaves the value F5H in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are all cleared.
Page 203 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats SET CARRY FLAG Set Carry Flag Instruction Format: Operation: C <— 1 The C Flag is set to 1, regardless of its previous value. Flags: Set to 1 Unaffected Unaffected Unaffected Unaffected Unaffected...
Page 204 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG SHIFT RIGHT ARITHMETIC Shift Right Arithmetic SRA dst Instruction Format: Operation: C <— dst(0) dst(0) <— dst(1) dst(1) <— dst(2) dst(2) <— dst(3) dst(3) <— dst(4) dst(4) <— dst(5) dst(5) <— dst(6) dst(6) <— dst(7) dst(7) <—...
Page 205 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats SHIFT RIGHT ARITHMETIC Example: If the contents of Working Register R6 are 31H (00110001B), the statement: SRA R6 Op Code: D0 E6 leaves the value 98H (00011000) in Working Register R6. The C Flag is set, and the Z, V, and S Flags are cleared.
Page 206 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG SET REGISTER POINTER Set Register Pointer SRP src Instruction Format: Operation: RP <— src The specified value is loaded into the Register Pointer (RP) (Control Register FDH). Bits 7-4 determine the Working Register Group. Bits 3-0 selects the Expanded Register Bank. Addressing of un-implemented Working Register Group, while using Expanded Register Banks, will point to Bank 0.
Page 207 Unaffected Note: When an Expanded Register Bank , other than Bank 0 is selected, access to the Z8 Standard Register File is possible except for the Port Register and general purpose registers 04H to 0FH. fpr Register Addresses 0H to FH.
Page 208 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG SET REGISTER POINTER Example: Assume the RP currently addresses the Control and Peripheral Working Register Group and the program has just entered an interrupt service routine. The statement: SRP 70H Op Code: 31 70 retains the contents of the Control and Peripheral Registers by setting the RP to 70H (01110000B).
Page 209 In order to enter STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP immediately before the execution of the STOP instruction. Example: The statements: STOP Op Codes: FF 6F place the Z8 into STOP mode. UM001601-0803 12-69...
Page 210 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG SUBTRACT Subtract SUB dst, src Instruction Format: Operation: dst <— dst - src The source operand is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed by adding the two’s complement of the source operand to the destination operand.
Page 211 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats SUBTRACT Example: If Working Register R15 contains 16H, Working Register R10 contains 20H, and Register 20H contains 11H, the statement: SUB R16, @R10 Op Code: 23 FA leaves the value 05H in Working Register R15. The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
Page 212 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG SWAP SWAP NIBBLES SWAP Swap Nibbles SWAP dst Instruction Format: Operation: dst(7-4) <—> dst(3-0) The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: Unaffected Set if the result is zero;...
Page 213 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats TEST COMPLEMENT UNDER MASK Test Complement Under Mask TCM dst, src Instruction Format: Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask).
Page 214 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG TEST COMPLEMENT UNDER MASK Example: If Working Register R3 contains 45H (01000101B) and Working Register R7 contains the value 01H (00000001B) (bit 0 is being tested if it is 1), the statement: TCM R3, R7 Op Code: 62 37 will set the Z Flag indicating bit 0 in the destination operand is 1.
Page 215 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats TEST UNDER MASK Test Under Mask TM dst, src Instruction Format: Operation: dst AND src This instruction tests selected bits in the destination operand for a 0 logical value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask).
Page 216 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG TEST UNDER MASK Example Working Register R14 contains the value F3H (11110011B), Working Register R5 contains CBH, and Register CBH contains 88H (10001000B) (bit 7 a bit 3 are being tested if they are 0), the statement:...
Page 217 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats WATCH-DOG TIMER ENABLE DURING HALT MODE Watch-Dog Timer Enable During HALT Mode Instruction Format: Operation: When this instruction is executed it will enable the WDT (Watch-Dog Timer) during HALT mode. If this instruction is not executed the WDT will stop when entering HALT mode. This instruction does not clear the counter, it just makes it possible to have the WDT function running during HALT mode.
Page 218 Instruction Format: Operation: The WDT (Watch-Dog Timer) is a retriggerable one shot timer that will reset the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction. Each subsequent execution of the WDT instruction refreshes the timer and prevents the WDT from timing out.
Page 219 Z8 Microcontrollers ZiLOG Instruction Descriptions and Formats LOGICAL EXCLUSIVE OR Logical Exclusive OR XOR dst, src Instruction Format: Operation: dst <— dst XOR src The source operand is logically EXCLUSIVE ORed with the destination operand. The XOR operation results in a 1 being stored in the destination operand whenever the corresponding bits in the two operands are different, otherwise a 0 is stored.
Page 220 Z8 Microcontrollers Instruction Descriptions and Formats ZiLOG LOGICAL EXCLUSIVE OR Example If Working Register R4 contains F9H (11111001B), Working Register R13 contains 7BH, and Register 7B contains 6AH (01101010B), the statement: XOR R4, @R13 Op Code: B3 4D leaves the value 93H (10010011B) in Working Register R4. The S Flag is set, and the Z, and V Flags are cleared.

ZiLOG Z8 User Manual

Chapter 1 . Z8 MCU Product Overview

Chapter 2 . Address Space

Chapter 3. Clock

Chapter 4 . Reset-Watch-Dog Timer

Chapter 5. I/O Ports

Zilog

Chapter 6 . Counter/Timers

Chapter 7. Interrupts

Chapter 8 . Power-Down Modes

Chapter 9. Serial I/O

Chapter 10 . External Interface

Chapter 11 . Addressing Modes

Chapter 12 . Instruction Set

Quick Links

Need help?

Questions and answers

Related Manuals for ZiLOG Z8

Summary of Contents for ZiLOG Z8

Table of Contents