ZiLOG Z8 User Manual page 164

Z8 Microcontrollers
Instruction Descriptions and Formats
DA
Decimal Adjust
DA dst
Instruction Format:
Operation:
dst <— DA dst
The destination operand is adjusted to form two 4-bit BCD digits following a binary addition or subtraction
operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the following table
indicates the operation performed.
Instruction
ADD
ADC
SUB
SBC
If the destination operand is not the result of a valid addition or subtraction of BCD digits, the operation is
undefined.
Flags: C: Set if there is a carry from the most significant bit; cleared otherwise (see table above).
Z: Set if the result is zero; cleared otherwise.
S: Set if result bit 7 is set (negative); cleared otherwise.
D Unaffected
H: Unaffected
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working
Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op Code.
12-24
Carry Bits 7-4
Before Value
DA (HEX)
0 0-9
0 0-8
0 0-9
0 A-F
0 9-F
0 A-F
1 0-2
1 0-2
1 0-3
0 0-9
0 0-8
1 7-F
1 6-F
H Flag Bits 3-0
Before Value
DA (HEX)
0 0-9
0 A-F
1 0-3
0 0-9
0 A-F
1 0-3
0 0-9
0 A-F
1 0-3
0 0-9
1 6-F
0 0-9
1 6-F
ZiLOG
DECIMAL ADJUST
Number Carry
Added To After
Byte DA
00 0
06 0
06 0
60 1
66 1
66 1
60 1
66 1
66 1
00 0
FA 0
A0 1
9A 1
UM001601-0803
DA