ZiLOG Z8 User Manual page 40

Z8 Microcontrollers
Reset—Watch-Dog Timer
4.2 RESET PIN, INTERNAL POR OPERATION (Continued)
Table 4-1. Sample Control and Peripheral Register Reset Values (ERF Bank 0)
Register Register
(HEX) Name
F0 Serial I/O
F1 Timer Mode
F2 Counter/Timer1
F3 T1 Prescaler
F4 Counter/Timer0
F5 T0 Prescaler
F6 Port 2 Mode
F7 Port 3 Mode
F8 Port 0–1 Mode
F9 Interrupt Priority
FA Interrupt Request
FB Interrupt Mask
FC Flags
FD Register Pointer
FE Stack Pointer (High)
FF Stack Pointer (Low)
Program execution starts 5 to 10 clock cycles after internal
RESET has returned High. The initial instruction fetch is from
location 000CH. Figure 4-1 shows reset timing.
Clock
SCLK
RESET
AS
DS
R/W
After a reset, the first routine executed should be one that initial-
izes the control registers to the required system configuration.
4-2
Bits
7 6 5 4 3 2
U U U U U U U U
0 0 0 0 0 0
U U U U U U U U
U U U U U U
U U U U U U U U
U U U U U U U
1 1 1 1 1 1
0 0 0 0 0 0
0 1 0 0 1 1
U U U U U U U U
0 0 0 0 0 0
0 U U U U U U U Interrupts Disabled
U U U U U U U U
0 0 0 0 0 0
U U U U U U U U
U U U U U U U U
Hold Low For 4 SCLK
Periods (Minimum)
Figure 4-1. Reset Timing
1 0 Comments
0 0 Counter/Timers Stopped
0 0 Single-Pass Count Mode, External Clock Source
0 Single-Pass Count Mode
1 1 All Inputs
0 0 Port 2 Open-Drain, P33–P30 Input, P37–P34 Output
0 1 Internal Stack, Normal Memory Timing
0 0 All Interrupts Cleared
0 0
The RESET pin is the input of a Schmitt-triggered circuit. Reset-
ting the Z8 will initialize port and control registers to their de-
First Machine Cycle
T1
First Instruction Fetch
UM001601-0803
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