ZiLOG
9.10 RECEIVE CHARACTER AVAILABLE AND OVERRUN
When a complete data stream is received, an interrupt is gener-
ated and the RxCharAvail bit in the SCON Register is set. Bit 4
in the SCON Register is for enabling or disabling the RxCharA-
vail interrupt. The RxCharAvail bit is available for interrupt
polling purposes and is reset when the RxBUF Register is read.
RxCharAvail is generated in both master and slave modes.
While in slave mode, if the RxBUF is not read before the next
data stream is received and loaded into the RxBUF Register, Re-
ceive Character Overrun (RxCharOverrun) occurs. Since there is
no need for clock control in slave mode, bit D1 in the SPI Con-
SK
SS
4
D0
DI
UM001601-0803
trol Register is used to log any RxCharOverrun (Figure 9-14 and
Figure 9-15).
No
1
2
3
4
5
3
1
Figure 9-14. SPI Timing
Parameter
DI to SK Setup
SK to D0 Valid
SS to SK Setup
SS to D0 Valid
SK to DI Hold Time
TSK
2
5
Z8 Microcontrollers
Serial I/O
Min
Units
10
ns
15
ns
.5 Tsk
ns
15
ns
10
ns
9-11
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