External Clock Input Mode - ZiLOG Z8 User Manual

Z8 Microcontrollers
Counter/Timers
It is suggested that P31 be configured as an input line by setting
P3M Register bit 5 to 0, although T
configured as a handshake input.

6.5.1 External Clock Input Mode

The T External Clock Input Mode (TMR bit 5 and bit 4 both
IN
set to 0) supports counting of external events, where an event is
considered to be a High-to-Low transition on T
T
IN
Clock
6-8
is still functional if P31 is
IN
(Figure 6-15).
IN
P3
D
1
Internal
Clock
Figure 6-15. External Clock Input Mode
Each High-to-Low transition on T
quest IRQ2, regardless of the selected T
the enabled/disabled state of T1. IRQ2 must therefore be masked
or enabled according to the needs of the application.
Note: See the product data sheet for the minimum allowed T
external clock input period (T
TMR
D - D = 00
5 4
PRE1
D
ZiLOG
generates an interrupt re-
IN
mode or
IN
T ).
P IN
IRQ
T1
IRQ
UM001601-0803
IN
5
2