I/O Port Reset Conditions; Full Reset - ZiLOG Z8 User Manual

Z8 Microcontrollers
I/O Ports

5.7 I/O PORT RESET CONDITIONS

5.7.1 Full Reset

After a hardware reset, Watch-Dog Timer (WDT) reset, or a
Power-On Reset (POR), Port Mode Registers P01M, P2M, and
P3M are set as shown in Figures 5-27 through 5-22. Port 2 is
configured for input operation on all bits and is set for open-
drain (Figure 5-29). If push-pull outputs are desired for Port 2
outputs, remember to configure them using P3M. Please note
that a WDT time-out from Stop-Mode Recovery does not do a
full reset. Certain registers that are not reset after Stop-Mode Re-
covery will not be reset.
For the condition of the Ports after Stop-Mode Recovery, please
refer to specific device product specifications. In some cases, the
5-22
Register F8H
Port 0-1 Mode Register (P01M)
(Write-Only)
0 1 0 0 1 1 0 1
Figure 5-27. Port 0/1 Reset
Z8 has the P01M, P2M, and P3M control register set back to the
default condition after reset while others do not.
All special I/O functions of Port 3 are inactive, with P33–P30 set
as inputs and P37–P34 set as outputs (Figure 5-29).
Note: Because the types and amounts of I/O vary greatly among
the Z8 family devices, the user is advised to review the selected
device's product specifications for the register default state after
reset.
P0 - P0 Mode
0 3
00 = Output
01 = Input
1X = A - A
8 11
Stack Selection
0 = External
1 = Internal
P - P Mode
10 17
00 = Byte Output
01 = Byte Output
10 = AD - AD
0 7
11 = High Impedance AD - AD
0
AS DS R
A - A , , , /W
8 15
External Memory Timing
Normal = 0
Extended = 1
P0 - P0 Mode
4 7
Output = 00
Input = 01
A - A = 1X
12 15
7,
UM001601-0803
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