Interrupt Request (Irq) Register Logic And Timing - ZiLOG Z8 User Manual

Z8 Microcontrollers
Interrupts
7.3 INTERRUPT REQUEST REGISTER LOGIC AND TIMING
Figure 7-5 shows the logic diagram for the Interrupt Request
(IRQ) Register. The leading edge of the request will set the first
flip-flop, that will remain set until interrupt requests are sam-
pled.
Requests are sampled internally during the last clock cycle be-
fore an opcode fetch (Figure 7-6). External requests are sampled
two internal clocks earlier, due to the synchronizing flip-flops
shown in Figures 7-3 and 7-4.
IRQ - IRQ
0 5
7-4
Q
Sample
Clock
R
Figure 7-5. IRQ Register Logic
Mn M1
T1 T2 T3 T1 T2 T3 T1 T2 T3
Figure 7-6. Interrupt Request Timing
At sample time the request is transferred to the second flip-flop
in Figure 7-5, that drives the interrupt mask and priority logic.
When an interrupt cycle occurs, this flip-flop will be reset only
for the highest priority level that is enabled.
The user has direct access to the second flip-flop by reading and
writing the IRQ Register. IRQ is read by specifying it as the
source register of an instruction and written by specifying it as
the destination register.
S
R
From
Priority
Logic
M2
Interrupt Request
Sampled Internally
External Interrupt
Request Sampled
ZiLOG
To Mask
and
Q
Priority
Logic
UM001601-0803