ZiLOG Z8 User Manual page 181

ZiLOG
LDCI
LOAD CONSTANT AUTO-INCREMENT
LDCI
Load Constant Auto-increment
LDCI dst, src
Instruction Format:
Operation:
dst <— src
r <— r + 1
rr <— rr + 1
This instruction is used for block transfers of data between program memory and the Register File. The address of
the program memory location is specified by a Working Register Pair, and the address of the Register File location
is specified by Working Register. The contents of the source location are loaded into the destination location. Both
addresses in the Working Registers are then incremented automatically. The contents of the source operand are not
affected.
Flags: C: Unaffected
Z: Unaffected
S: Unaffected
V: Unaffected
D: Unaffected
H: Unaffected
Example:
If Working Register Pair R6-R7 contains 30A2H, program memory location 30A2H and 30A3H contain 22H and
BCH respectively, and Working Register R2 contains 20H, the statement:
loads the value 22H into Register 20H. Working Register Pair RR6 is incremented to 30A3H and Working Register
R2 is incremented to 21H. A second
loads the value BCH into Register 21H. Working Register Pair RR6 is incremented to 30A4H and Working Register
R2 is incremented to 22H.
UM001601-0803
dst src
OPC
src dst
OPC
LDCI @R2, @RR6
Op Code: C3 26
LDCI @R2, @RR6
Op Code: C3 26
Instruction Descriptions and Formats
OPC
Address Mode
Cycles (Hex)
dst
18 C2 Ir
18 D2 Irr
Z8 Microcontrollers
src
Irr
Ir
12-41