ZiLOG Z8 User Manual page 130

Z8 Microcontrollers
External Interface
Clock
A15-A8
AD7-AD0
AS
DS
R/W
DM
Timing is extended by setting bit D5 in the Port 0-1 Mode Reg-
ister (F8H) to 1 (Figure 10-9). After a RESET, this bit is set to 0.
10-8
Machine Cycle
T1
T2
A7-A0
Figure 10-8. Extended External Memory Write Cycle
TX
A15-A8
D7-D0 OUT
Write Cycle
Register F8H (P01M)
Port 0-1 Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 10-9. Extended Bus Timing
ZiLOG
T3
External Memory Timing
0 = Normal
1 = Extended
UM001601-0803