Reset Source; Boot Option; Table 7. 8 Mhz Crystal X2 Related Solder Bridges; Table 8. Boot-Related Switch - ST STM32303C-EVAL User Manual

Hardware layout and configuration
Table 7.
Solder bridge
SB14
SB15
2.4

Reset source

The reset signal of the STM32303C-EVAL evaluation board is low active and the reset
sources include:
Reset button (B1)
Debugging tools from JTAG/SWD connector (CN10) and ETM trace connector (CN9)
Daughter board from CN7
Embedded ST-LINK/V2
RS232 connector (CN8) for ISP
Note: The JP10 jumper must be closed for RESET handled by pin8 of RS232 connector, CN8
(CTS signal).
2.5

Boot option

The STM32303C-EVAL evaluation board can boot from:
the embedded user Flash
the system memory with boot loader for ISP
the embedded SRAM for debugging
The boot option is configured by setting switch SW1 (BOOT0) and bit 12 of USER OPTION
BYTES (BOOT1) in Small Information block (SIF). BOOT0 can also be configured via the
RS232 connector, CN8.
Table 8.
Switch
configuration
0 <----> 1
0 <----> 1
0 <----> 1
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8 MHz crystal X2 related solder bridges
PF0 is connected to the 8 MHz crystal when SB14 is open (default setting).
PF0 is connected to the extension connector CN7 when SB14 is closed. In such a
case, C51 and X2 must be removed to avoid disturbance due to the 8 MHz quartz.
PF1 is connected to the 8 MHz crystal when SB15 is open (default setting).
PF1 is connected to the extension connector CN7 when SB15 is closed. In such a
case, R205 must be removed.
Boot-related switch
bit 12 of USER OPTION
BYTES
X
SW1
0
SW1
1
SW1
Doc ID 023581 Rev 2
Description
STM32303C-EVAL boot
From the user Flash when SW1 is set as
shown to the left (default setting)
From the embedded SRAM when SW1 and
bit12 in USER OPTION BYTES are set as
shown to the left.
From the system memory when SW1 and
bit12 in USER OPTION BYTES are set as
shown to the left.
UM1567