Boot Option; Clock Source; Reset Source; Table 3. Boot Related Switches - ST STM3210C-EVAL User Manual

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Boot option

The STM3210C-EVAL board is able to boot from:
•
Embedded user Flash
•
System memory with boot loader for ISP
•
Embedded SRAM for debugging
The boot option is configured by setting switches SW1 (BOOT1) and SW2 (BOOT0).
The BOOT0 can be configured also via the RS-232 connector CN6 when JP18 is fitted.
Switch
STM3210C-EVAL boots from User Flash when SW2 is set as shown to
the right. SW1 setting does not matter in this configuration. (Default)
STM3210C-EVAL boots from System Memory when SW1 and SW2 are
SW1
set as shown:
and
SW2
STM3210C-EVAL boots from Embedded SRAM when SW1 and SW2
are set as shown:

Clock source

Two clock sources are available on the STM3210C-EVAL evaluation board for
STM32F107VCT and RTC is embedded.
•
X2, 32 kHz crystal for embedded RTC.
•
X3, 25 MHz crystal with socket for an STM32F107VCT microcontroller, it can be
removed from the socket when an internal RC clock is used.

Reset source

The reset signal of the STM3210C-EVAL board is active low and the reset sources include:
• Reset button, B1
• Debugging tools from JTAG connector CN13 and trace connector CN12
• Daughterboard from CN9
• RS-232 connector CN6 for ISP when JP19 is fitted.
Jumper
Enables reset of the STM32F107VCT embedded JTAG TAP controller each time a system
JP20 reset occurs. JP20 connects the TRST signal from the JTAG connection with the system
reset signal RESET#. Default setting: Not fitted.
Hardware layout and configuration

Table 3. Boot related switches

Boot from

Table 4. Reset related jumper

Description
DocID15082 Rev 5
Configuration
SW2
0 < > 1
SW1
SW2
0 < > 1
SW1
SW2
0 < > 1
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