Clock Source; Reset Source; Table 4. Boot Switches And Jumper - ST STM32100B-EVAL User Manual

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Table 4. Boot switches and jumper
Switch
STM32100B-EVAL boots from user Flash when SW2 is set as
shown to the right (default setting).
In this configuration, the position of SW1 does not affect the boot
process.
SW1
STM32100B-EVAL boots from embedded SRAM when SW1 and
SW2 are set as shown to the right.
SW2
STM32100B-EVAL boots from system memory when SW1 and
SW2 are set as shown to the right.
BOOT0 pin of the STM32F100VBT6 is connected to the RS-232
connector CN10 pin 8 (CTS) for ISP support when JP4 is closed.
JP4
This configuration is used for boot loader application only.
Default setting: not fitted.

Clock source

Two clock sources are available on the STM32100B-EVAL board for the STM32F100VBT6
microcontroller and RTC.
●
X1, 32 KHz crystal for embedded RTC
●
X2, 8 MHz crystal with socket for the STM32F100VBT6 microcontroller. It can be
removed from the socket when the internal RC clock is used.

Reset source

The reset signal of the STM32100B-EVAL board is active low and the reset sources include:
●
Reset button B1
●
Debugging tools from JTAG connector CN3
●
Daughterboard from CN5
●
Embedded ST-LINK
●
Bootloader_Reset from RS-232 connector CN10
Hardware layout and configuration
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Doc ID 16533 Rev 3
Switch configuration
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