Hardware layout and configuration
2.4
Note:
2.5
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Table 5. 32 kHz crystal X1 related solder bridges (continued)
Solder bridge
PC15 is connected to the 32 KHz crystal when SB13 is open (default setting).
SB13
PC15 is connected to the extension connector CN6 when SB13 is closed. In such
a case, R197 must be removed to avoid disturbance due to the 32 KHz quartz.
Table 6. 8 MHz crystal X2 related solder bridges
Solder bridge
PF0 is connected to the 8 MHz crystal when SB14 is open (default setting).
PF0 is connected to the extension connector CN7 when SB14 is closed. In such a
SB14
case, C51 and X2 must be removed to avoid disturbance due to the 8 MHz
quartz.
PF1 is connected to the 8 MHz crystal when SB15 is open (default setting).
SB15
PF1 is connected to the extension connector CN7 when SB15 is closed. In such a
case, R205 must be removed.
Reset source
The reset signal of the STM32303E-EVAL evaluation board is low active and the reset
sources include:
•
Reset button (B1)
•
Debugging tools from JTAG/SWD connector (CN10) and ETM trace connector (CN9)
•
Daughter board from CN7
•
Embedded ST-LINK/V2
•
RS232 connector (CN8) for ISP
The JP10 jumper must be closed for RESET handled by pin8 of RS232 connector, CN8
(CTS signal).
Boot option
The STM32303E-EVAL evaluation board can boot from:
•
the embedded user Flash
•
the system memory with boot loader for ISP
•
the embedded SRAM for debugging
The boot option is configured by setting switch SW1 (BOOT0) and bit 12 of USER OPTION
BYTES (BOOT1) in Small Information block (SIF). BOOT0 can also be configured via the
RS232 connector, CN8.
Description
Description
DocID026738 Rev 1
UM1807
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