Interrupt Mask: Msks(153) - Omron SYSMAC CV Series Operation Manual

Interrupt Control

5-31-1 INTERRUPT MASK: MSKS(153)

Ladder Symbol
(153)
MSKS
Variations
j MSKS(153)
Description
Precautions
Flags
N S
When the execution condition is OFF, MSKS(153) is not executed. When the ex-
ecution condition is ON, MSKS(153) masks interrupts from Interrupt Input Units
(so that they are recorded but ignored) if N is 0 to 3 or sets the time interval for
scheduled interrupts if N is 4 or 5.
N specifies the interrupt. Numbers 0 to 3 indicate I/O Interrupt Input Units 0 to 3,
and numbers 4 and 5 indicate scheduled interrupts 0 and 1, respectively. The
CV500 or CVM1-CPU01-EV2 has scheduled interrupt 0 only.
If N is 0 to 3, it designates an Interrupt Input Unit, and MSKS(153) causes the bits
of the designated Interrupt Input Unit corresponding to ON bits in S to be
masked, and those corresponding to OFF bits in S to be unmasked. All masked
interrupts will still be recorded. When a masked bit has been recorded as being
ON, the interrupt program for it will be run as soon as the bit is unmasked (unless
it is cleared first; see 5-31-2 CLEAR INTERRUPT: CLI(154) ). All interrupts are
initially masked.
If N is 4 or 5, it designates a scheduled interrupt and MSKS(153) sets the time
interval for the scheduled interrupt. The interval between interrupts can be set
between 10 and 99,990 ms, depending on both the content of S and the time unit
set in the PC Setup. S can have any value between 0001 and 9999, and time
units can be and set to 0.5 ms, 1 ms, or 10 ms.
To cancel the scheduled interrupt, execute MSKS(153) with S set to 0000. This
is the initial setting. Refer to 5-31-2 CLEAR INTERRUPT: CLI(154) for an exam-
ple of scheduled interrupts.
CLI(154) should be used to set the time to the first scheduled interrupt. Unstable
operation may result if the time to the first interrupt is not set. Refer to 5-31-2
CLEAR INTERRUPT: CLI(154) .
N must be between 0 and 5 for the CV1000, CV2000, CVM1-CPU11-EV2, or
CVM1-CPU21-EV2 or between 0 and 4 for the CV500 or CVM1-CPU01-EV2.
S must be between 0000 and 00FF when N is between 0 and 3. S must be BCD
between 0001 and 9999 when N is 4 or 5.
I/O interrupts and scheduled interrupts are masked when power is turned on or
the PC mode is changed.
Both the scheduled interrupt time and the time to the first scheduled interrupt
must be 10 ms or greater.
Note Refer to page 115 for general precautions on operand data areas.
ER (A50003): N or S contain improper data
(e.g., data in S is not BCD when N is 4 or 5).
Content of *DM word is not BCD when set for BCD.
A value of 5 is entered for N in the CV500 or
CVM1-CPU01-EV2.
Operand Data Areas
N: Interrupt source # (0 to 5)
S: Data source word CIO, G, A, T, C, #, DM, DR, IR
Section 5-31
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