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Omron SYSMAC CV Series Operation Manual

Omron SYSMAC CV Series Operation Manual

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SYSMAC CV-series

CV500/CV1000/CV2000/CVM1

Programmable Controllers

Operation Manual: Ladder Diagrams

Revised August 1998

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Page 1 SYSMAC CV-series CV500/CV1000/CV2000/CVM1 Programmable Controllers Operation Manual: Ladder Diagrams Revised August 1998...
Page 3 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice.
Page 5: Table Of Contents
............OMRON Product Terminology .
Page 6 TABLE OF CONTENTS SECTION 4 Writing Programs ....... Basic Procedure .
Page 7 TABLE OF CONTENTS SECTION 6 Program Execution Timing ......PC Operation ............Cycle Time .
Page 8 About this Manual: This manual describes ladder diagram programming and memory allocation in the SYSMAC CV-series Program- mable Controllers (PCs) (CV500, CV1000, CV2000, and CVM1). This manual is designed to be used together with two other CV-series PC operation manuals and an installation guide. The entire set of CV-series PC manuals is listed below.
Page 9 PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the Programmable Con- troller. You must read this section and understand the information contained before attempting to set up or operate a PC system.
Page 10: Intended Audience
It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the above-mentioned applications.
Page 11: Operating Environment Precautions
Application Precautions Operating Environment Precautions Caution Do not operate the control system in the following places: Locations subject to direct sunlight. Locations subject to temperatures or humidity outside the range specified in the specifications. Locations subject to condensation as the result of severe changes in tempera- ture.
Page 12 Application Precautions Interlock circuits, limit circuits, and similar safety measures in external circuits (i.e., not in the Programmable Controller) must be provided by the customer. Always use the power supply voltage specified in the operation manuals. An incorrect voltage may result in malfunction or burning. Take appropriate measures to ensure that the specified power with the rated voltage and frequency is supplied.
Page 13: Introduction
It also provides an overview of the process of programming and operating a PC and ex- plains basic terminology used with OMRON PCs. A list of the manuals available to use with this manual for special PC applications and products is also provided.
Page 14: Overview
Overview Section 1-1 Overview A PC (Programmable Controller) is basically a CPU (Central Processing Unit) containing a program and connected to input and output (I/O) devices. The pro- gram controls the PC so that when an input signal from an input device turns ON or OFF, the appropriate response is made.
Page 15: Relay Circuits: The Roots Of Pc Logic
The terminology used throughout this manual is somewhat different from relay terminology, but the concepts are the same. The following table shows the relationship between relay terms and the PC terms used for OMRON PCs. Relay term PC equivalent contact...
Page 16: Omron Product Terminology
Appendix A Standard Models lists products according to these groups. The term Unit is used to refer to all of the OMRON PC products. Although a Unit is any one of the building blocks that goes together to form a CV-series PC, its meaning is generally, but not always, limited in context to refer to the Units that are mounted to a Rack.
Page 17 Overview of PC Operation Section 1-5 3. On paper, assign all input and output devices to I/O points on Units and de- termine which I/O bits will be allocated to each. If the PC includes Special I/O Units, CPU Bus Units, or Link Systems, refer to the individual Operation Manuals or System Manuals for details on I/O bit allocation.
Page 18: Pc Operating Modes
PC Operating Modes Section 1-6 Input/Output Requirements The first thing that must be assessed is the number of input and output points that the controlled system will require. This is done by identifying each device that is to send an input signal to the PC or which is to receive an output signal from the PC.
Page 19: Peripheral Devices
Peripheral Devices Section 1-7 Peripheral Devices The CV Support Software (CVSS) and the SYSMAC Support Software (SSS) are the main Peripheral Device used to program and monitor CV-series PCs. You must have the CVSS/SSS to program and operate these PCs. The following Peripheral Devices are available for basic programming/monitoring.
Page 20: Cv-Series Manuals
CV-series Manuals Section 1-8 CV-series Manuals The following manuals are available for CV-series products. Manuals are also available for compatible C-series products (see next section). Catalog number suffixes have been omitted; be sure you have the current version for your region. Product Manual Cat.
Page 21: C-Series-Cv-Series System Compatibility
C-series – CV-series System Compatibility Section 1-9 C-series–CV-series System Compatibility The following table shows when C-series Units can be used and when CV-series Units must be used. Any C-series Unit or Peripheral Device not listed in this table cannot be used with the CV-series PCs. Unit C Series CV Series...
Page 22: Networks And Remote I/O Systems
Networks and Remote I/O Systems Section 1-10 1-10 Networks and Remote I/O Systems Systems that can be used to create networks and enable remote I/O are introduced in this section. Refer to the operation manuals for the Systems for details. SYSMAC NET Link System The SYSMAC NET Link System is a LAN (local area network) for use in factory automation systems.
Page 23 Networks and Remote I/O Systems Section 1-10 SYSMAC LINK System Networks can also be created using SYSMAC LINK Systems. A SYSMAC LINK System can consist of up to 62 PCs, including the CV500, CV1000, CV2000, CVM1, C200H, C1000H, and C2000H. Communications between the PCs is ac- complished via datagrams, data transfers, or automatic data links in ways simi- lar to the SYSMAC NET Link System.
Page 24 Networks and Remote I/O Systems Section 1-10 SYSMAC BUS/2 Remote I/O Remote I/O can be enabled by adding a SYSMAC BUS/2 Remote I/O System to System the PC. The SYSMAC BUS/2 Remote I/O System is available in two types: opti- cal and wired.
Page 25 Networks and Remote I/O Systems Section 1-10 SYSMAC BUS Remote I/O Remote I/O can also be enabled by using the C-series SYSMAC BUS Remote System I/O System with CV-series PC. Remote I/O Master Units can be mounted on any slot of the CPU Rack, Expan- sion CPU Rack, or Expansion I/O Rack.
Page 26 Networks and Remote I/O Systems Section 1-10 Host Link System The CV-series PCs can be connected to a host computer with the host link con- (SYSMAC WAY) nector via the CPU or a CV500-LK201 Host Link Unit mounted to a Rack. RS-232C or RS-422 communications can be used depending on the switch set- ting.
Page 27: New Cpus And Related Units
New CPUs and Related Units Section 1-11 Data can also be transferred to other BASIC Units mounted on the same PC, or to BASIC Units mounted to other PCs connected by networks formed using a SYSMAC NET Link or SYSMAC LINK System. RS-232C, RS-422, Centronics, and GPIB interfaces are available.
Page 28: Cpu Comparison
Improved Specifications Section 1-13 1-12 CPU Comparison The following table shows differences between the various CV-series CPUs. CVM1- CVM1- CVM1- CV500- CV1000- CV2000- CPU01-EV2 CPU11-EV2 CPU21-EV2 CPU01-EV1 CPU01-EV1 CPU01-EV1 Ladder diagrams Supported Supported Supported Supported Supported Supported Program- Not supported Not supported Not supported Supported...
Page 29 Improved Specifications Section 1-13 3. The operation of Completion Flags for timers has been changed so that the Completion Flag for a timer turns ON only when the timer instruction is executed with a PV of 0000 and not when the timer’s PV is refreshed to a PV value of 0000, as was previously done.
Page 30 Improved Specifications Section 1-13 1-13-3 Version-2 CVM1 CPUs CVM1 CPUs were changed to version 2 and a new CPU was added from De- cember 1994. The new model numbers are as follows: CVM1-CPU01-EV2, CVM1-CPU11-EV2, and CVM1-CPU21-EV2. The following additions and improvements were made to create the version-2 CPUs.
Page 31 Improved Specifications Section 1-13 1-13-4 Upgraded Specifications The following improvements were made December 1995 and are applicable to CV500/CV1000/CV2000-CPU01-EV1 CVM1-CPU01/CPU11/CPU21-EV2 CPUs with lot numbers in which the rightmost digit is 6 (jjj6) or higher. Simplified Backup Function Added Specifications have been changed so that the user program, Extended PC Set- up, and IOM/DM data can be backed up from memory in the CPU Unit to a Memory Card without using a Programming Device, and so that the data backed up in the Memory Card can be transferred back to memory in the CPU Unit with-...
Page 32 The following commercially available memory cards can be used. The proce- dures and applications for using these memory cards is exactly the same as for the Memory Cards provided by OMRON. RAM Memory Cards conforming to JEIDA4.0 and of the following sizes: 64 Kbytes, 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, and 2 Mbytes.
Page 33: Hardware Considerations
SECTION 2 Hardware Considerations This section provides information on hardware aspects of CV-series PCs that are relevant to programming and software op- eration. These include indicators on the CPU and basic PC configuration. This information is covered in more detail in the CV-series PC Installation Guide.
Page 34: Cpu Components
CPU Components Section 2-1 CPU Components The following diagram shows the basic components of the CPU that are used in general operation of the PC. Indicators Protect keyswitch Used to write-protect the Pro- gram Memory (i.e., the Ex- tended PC Setup and the user program).
Page 35: Switches
CPU Components Section 2-1 2-1-2 Switches The DIP switch and memory card power switch are shown below and the setting of these and the other CPU switches are described in the following table. Switches are the same for all CV-series PCs. Switch Position Function...
Page 36: Program Memory
Program Memory Section 2-2 Program Memory Program Memory is contained in the CPU and is divided into two areas, the PC Setup and the Program Area. There are 32K words of Program Memory avail- able in the CV500, CVM1-CPU01-EV2, or CVM1-CPU11-EV2, and 64K words available in the CV1000, CV2000, or CVM1-CPU21-EV2.
Page 37: Memory Cards
CPUs with lot numbers in which the rightmost digit is 6 (jjj6) or higher. The procedures and applications for using these memory cards is exactly the same as for the Memory Cards provided by OMRON. RAM Memory Cards conforming to JEIDA4.0 and of the following sizes: 64 Kbytes, 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, and 2 Mbytes.
Page 38: File Transfer Between The Cpu And Memory Card
Memory Cards Section 2-3 4. Close the cover. Memory Card indicator Memory Card ON/OFF switch Memory Card eject button Memory Card Cover Removing a Memory Card 1, 2, 3... 1. Open the cover of the Memory Card compartment. 2. Press the Memory Card ON/OFF switch once if the Memory Card indicator is lit.
Page 39 Memory Cards Section 2-3 Communications Unit settings, BASIC Unit memory switches, and custom- ized settings (function codes and data areas). 2. The files that will be transferred at start-up must be named “AUTOEXEC.” 3. Files called BACKUP are created when the simplified backup function is used.
Page 40: Data Memory And Expansion Data Memory Unit
Data Memory and Expansion Data Memory Unit Section 2-4 Memory Card Writer Operation Manual for details. Set the drive name to “0” when accessing a Memory Card. The RAM and EEPROM cards have a write-protect switch, as shown in the dia- gram below.
Page 41: I/O Control Unit And I/O Interface Unit Displays
I/O Control Unit and I/O Interface Unit Displays Section 2-5 current bank number can be changed with the EMBC(171) instruction. Refer to Section 5 Instruction Set for details. There are three models of EM Units available, as shown in the following table. Model Memory capacity Memory banks...
Page 42 I/O Control Unit and I/O Interface Unit Displays Section 2-5 Display Mode 1 In mode 1, the first I/O word allocated to that Rack is displayed. If the I/O table hasn’t been registered yet, or an error occurred during registration, the display will show “0000.”...
Page 43: Peripheral Devices
PC Configuration Section 2-7 tination unit can be changed to mode 3 automatically by the instruction. Refer to Section 5 Instruction Set for details on IODP(189). Display Mode 4 Mode 4 is not being used currently. In mode 4, the display will show only the deci- mal point indicating it is in mode 4.
Page 44 PC Configuration Section 2-7 executes the program and controls the PC. (3) Other Units, such as I/O Units, Special I/O Units, and Link Units, which provide the physical I/O terminals corre- sponding to I/O points. (4) The I/O Control Unit which provides connections to an Expansion CPU Rack and Expansion I/O Racks.
Page 45: Memory Areas
SECTION 3 Memory Areas This section describes the way in which PC memory is broken into various areas used for different purposes. The contents of each area and addressing conventions, including the use of indirect addressing and addressing registers, are also described. Introduction .
Page 46 3-6-33 CPU Bus Unit Setting Error Flag and Unit Number ..... . 3-6-34 Battery Low Flags ..........3-6-35 SYSMAC BUS Error Flag, Check Bits, and Master/Unit Numbers .
Page 47: Introduction
Introduction Section 3-1 Introduction Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally ac- cessible by the user for use in programming are classified as data areas.
Page 48: Data Area Structure
Data Area Structure Section 3-2 Flags and Control Bits Some data areas contain flags and/or control bits. Flags are bits that are au- tomatically turned ON and OFF to indicate particular operation status. Al- though some flags (e.g., the Carry Flag) can be turned ON and OFF by the user, most flags are read only;...
Page 49 Data Area Structure Section 3-2 The same timer and counter numbers can be used to designate either the present value (PV) of the timer or counter, or the Completion Flag for the tim- er or counter. This is explained in more detail in 3-9 Timer Area and 3-10 Counter Area .
Page 50 Unsigned binary Unsigned binary is the standard format used in OMRON PCs. Data in this manu- al are unsigned unless otherwise stated. Unsigned binary values are always positive and range from 0 ($0000) to 65,535 ($FFFF). Eight-digit values range from 0 ($0000 0000) to 4,294,967,295 ($FFFF FFFF).
Page 51 Data Area Structure Section 3-2 Converting Decimal to Positive signed binary data is identical to unsigned binary data (up to 32,767) Signed Binary and can be converted using BIN(100). The following procedure converts nega- tive decimal values between –32,768 and –1 to signed binary. In this example –12345 is converted to CFC7.
Page 52: Cio (Core I/O) Area
CIO (Core I/O) Area Section 3-3 CIO (Core I/O) Area CIO Area addresses run from words CIO 0000 through CIO 2555 and bits CIO 000000 through CIO 255515 and are divided into eight data areas. Five of these data areas are used to control I/O points and Special Units, and three data areas are used to manipulate and store data internally.
Page 53: I/O Area
CIO (Core I/O) Area Section 3-3 Area Range Function Work Words: CIO 1964 to CIO 1999 These bits are used in the program to Areas Bits: CIO 196400 to CIO 199915 manipulate or to temporarily store data. ($07AC to $07CF) These bits can be set as holding bits via the PC Setup.
Page 54 CIO (Core I/O) Area Section 3-3 used in only one instruction that controls its status, including OUT, KEEP(11), DIFU(13), DIFD(14), and SFT(10). If an output bit is used in more than one such instruction, only the status determined by the last instruction will actual- ly be output from the PC during the normal I/O refresh period.
Page 55 CIO (Core I/O) Area Section 3-3 Unit Words required Position Control Units (See note 2) NC111/NC103/NC112/NC121: 4 words NC222: 2 words I/O Interface Unit None Cam Positioner 2 or 4 words Ladder Program I/O Unit 2 words ASCII Unit (ASC03 not applicable; use 2 or 4 words ASC04.) SYSMAC NET Link Unit...
Page 56 CIO (Core I/O) Area Section 3-3 on the left of the CPU Rack is an Input Unit, the top terminals (i.e., the top input point) will be assigned CIO 000000, the next terminals, CIO 000001, and so forth for all of the terminals on the Unit. The allocation order is illus- trated below.
Page 57: Work Areas
CIO (Core I/O) Area Section 3-3 ating an I/O verification error. Dummy I/O Units are available to fill slots for future use or to replace Units that are no longer needed (see Word Reserva- tions , below). There are two ways, however, to change the I/O table registered in memory. One is to allocate words to a slot that is not currently being used.
Page 58: Sysmac Bus/2 Area
CIO (Core I/O) Area Section 3-3 Work words and bits are reset when power is interrupted or PC operation is stopped, but they are not reset when a FALS error instruction is executed in the program. Work words Work bits CV500 CIO 0032 to CIO 0199 CIO 003200 to CIO 019915...
Page 59: Holding Area
CIO (Core I/O) Area Section 3-3 either a SYSMAC LINK System or a SYSMAC NET Link System. Link Area addresses run from CIO 1000 through CIO 1199. Link Area words CIO 1000 through CIO 1063 and DM Area words D00000 through D00127 are auto- matically used for data link tables unless specific link words are designated.
Page 60: Tr (Temporary Relay) Area
TR (Temporary Relay) Area Section 3-4 3-3-8 SYSMAC BUS Area I/O bits allocated in the SYSMAC BUS Area correspond to external I/O points on I/O Terminals, Optical I/O Units, or I/O Units mounted to Slave Racks that are connected to SYSMAC BUS Remote I/O Master Units (RM). Up to 8 Masters can be connected to the CV1000, CV2000, CVM1-CPU11-EV2, or CVM1-CPU21-EV2, and up to 4 Masters can be connected to the CV500 or CVM1-CPU01-EV2.
Page 61: Cpu Bus Link Area
CPU Bus Link Area Section 3-5 CPU Bus Link Area The CPU Bus Link Area is indicated by a G prefix. Addresses range from G000 to G255. The CPU Bus Link Area can be divided into 3 sections, the PC Status Area, Clock/Calendar Area, and Data Link Area.
Page 62: Auxiliary Area
Auxiliary Area Section 3-6 Data Link Area The CPU Bus Link Area is disabled by default in the PC Setup and must be enabled with the CVSS/SSS in order to use the Data Link Area. The 120 words of CPU Bus Link Area from G008 to G127 are used for outputs from the CPU to BASIC Units.
Page 63 Auxiliary Area Section 3-6 Word(s) Bit(s) Function A006 00 to 15 Not used. A007 00 to 15 Momentary Power Interruption Time (BCD) A008 00 to 06 Not used. Stop Monitor Flag Execution Time Measured Flag Differentiate Monitor Completed Flag Stop Monitor Completed Flag Trace Trigger Monitor Flag Trace Completed Flag Trace Busy Flag...
Page 64 Auxiliary Area Section 3-6 Word(s) Bit(s) Function 08 to 15 Peripheral Connected Flags for RT #0 to RT #7 of RM/2 #1 A308 00 to 07 Peripheral Connected Flags for RT #0 to RT #7 of RM/2 #2 08 to 15 Peripheral Connected Flags for RT #0 to RT #7 of RM/2 #3 A309...
Page 65 Auxiliary Area Section 3-6 Word(s) Bit(s) Function A403 00 to 08 Memory Error Area Location Memory Card Startup Transfer Error Flag 10 to 15 Not used. A404 00 to 07 I/O Bus Error Slot Number (BCD) 08 to 15 I/O Bus Error Rack Number (BCD) A405 00 to 15 CPU Bus Unit Error Unit Number...
Page 66: Restart Continuation Bit
Auxiliary Area Section 3-6 Word(s) Bit(s) Function A500 00 to 02 Not used. Instruction Execution Error Flag Carry Flag Greater Than Flag Equals Flag Less Than Flag Negative Flag Overflow Flag Underflow Flag Not used. First Cycle Flag when one-step operation is started with STEP instruction Always ON Flag Always OFF Flag...
Page 67: Forced Status Hold Bit
Auxiliary Area Section 3-6 If the IOM Hold Bit is ON, and the status of the IOM Hold Bit itself is pre- served in the PC Setup (Setting B, IOM Hold Bit status), then I/O Memory is also preserved when the PC is turned ON or power is interrupted. 3-6-3 Forced Status Hold Bit Bit A00013 can be turned ON to preserve the status of bits that have been force-set or force-reset when switching modes (except RUN mode).
Page 68: Cvss/Sss Flags
Auxiliary Area Section 3-6 The power interruption time is output to words A012 and A013, and the number of power interruptions is output to word A014. 3-6-9 CVSS/SSS Flags Word A008 contains flags that indicate the status of commands and instructions performed with the CVSS/SSS.
Page 69: Number Of Power Interruptions
Auxiliary Area Section 3-6 3-6-12 Number of Power Interruptions Word A014 contains the number of times that power has been interrupted since the PC was first turned on. The number is in BCD, and can be reset by writing #0000 to word A014. 3-6-13 Service Disable Bits Words A015 and A017 contain control bits that disable I/O servicing to certain Units and periodic refreshing.Turn these bits ON and OFF in the program.
Page 70: Cpu Bus Unit Initializing Flags
Auxiliary Area Section 3-6 Record Addresses Pointer value* A145 to A149 000A A150 to A154 000B A155 to A159 000C A160 to A164 000D A165 to A169 000E A170 to A174 000F A175 to A179 0010 A180 to A184 0011 A185 to A189 0012 A190 to A194...
Page 71: Peripheral Device Flags
Auxiliary Area Section 3-6 I/O Verification Error Wait Bit A30601 is ON when the PC is not running because an I/O Verification Er- Flag (A30601) ror has occurred, and the PC Setup are set so the PC does not run when an I/O Verification Error occurs.
Page 72: Error Code
Auxiliary Area Section 3-6 File Missing Flag (A34311) Bit A34311 is turned ON when the specified file is not on the installed card or no card is installed. Memory Card Write Flag Bit A34312 is turned ON when the Memory Card is being written to from the (A34312) program (FILW(181)).
Page 73: Cpu Bus Error And Unit Flags
Auxiliary Area Section 3-6 pansion Racks is written to word A407; in the SYSMAC BUS/2 system, to word A408; and in the SYSMAC BUS system, to word A478. 3-6-28 CPU Bus Error and Unit Flags Bit A40112 is turned ON when an error occurs during the transmission of data between the CPU and CPU Bus Units, or a WDT (watchdog timer) error occurs in a CPU Bus Unit.
Page 74: Battery Low Flags
Auxiliary Area Section 3-6 3-6-34 Battery Low Flags Bit A40204 is turned ON if the voltage of the CPU or Memory Card battery drops. If the problem has occurred with the Memory Card battery, bit A42614 will be turned ON, and if the problem has occurred with the CPU battery, bit A42615 will be turned ON.
Page 75: Cpu Bus Unit Error Flag And Unit Numbers
Auxiliary Area Section 3-6 Information identifying the Slave Unit(s) involved is contained in words A480 through A499, which are divided into four groups of five words, one group for each Master, as shown below. Words Master number A480 to A484 A485 to A489 A490 to A494 A495 to A499...
Page 76: Memory Error Area Location
Auxiliary Area Section 3-6 3-6-43 Memory Error Area Location Bits A40300 to A40308 are turned ON to indicate the memory area in which a memory error has occurred. The bits correspond to memory areas as follows: 00: Program Memory 05: I/O Table 01: Memory Card 06: System Memory 02: I/O Memory...
Page 77: Arithmetic Flags
Auxiliary Area Section 3-6 word that is non-existent. When the ER Flag is ON, the current instruction will not be executed. 3-6-51 Arithmetic Flags The following flags are used in data shifting, arithmetic calculation, and com- parison instructions. They are generally referred to only by their two-letter abbreviations.
Page 78: Transition Area
Transition Area Section 3-7 Note Do not use A50015 to control execution of differentiated instructions. The instructions will never be executed. 3-6-54 Clock Pulse Bits Four clock pulses are available to control program timing. Each clock pulse bit is ON for the first half of the rated pulse time, then OFF for the second half.
Page 79: Step Area
Timer Area Section 3-9 Input the transition number as a bit operand when designating Transition Flags in instructions. The CVM1 does not support SFC programming and is not equipped with a Tran- sition Area. Step Area A step in the program represents a single process. All SFC programs are executed by step.
Page 80: Counter Area
DM and EM Areas Section 3-11 3-10 Counter Area Counter Completion Flags and present values (PV) are accessed through counter numbers ranging from C0000 through C0511 for the CV500 or CVM1-CPU01-EV2 and from C0000 through C1023 for the CV1000, CV2000, CVM1-CPU11-EV2, or CVM1-CPU21-EV2. Each counter number and its set value (SV) are defined using counter instructions.
Page 81 DM and EM Areas Section 3-11 Although composed of 16 bits just like any other word in memory, DM and EM words cannot be specified by bit for use in instructions with bit-size oper- ands, such as LD, OUT, AND, and OR, nor can DM words be used with the SHIFT instruction.
Page 82: Index And Data Registers (Ir And Dr)
Index and Data Registers (IR and DR) Section 3-12 Word Content (030) MOV *D00100 A090 D00099 4C59 D00100 0200 Indirect Indicates D00101 F35A address CIO 0512. CIO 0512 5555 CIO 0513 2506 5555 moved to A090. CIO 0514 D541 Indirect addressing can also be used in instructions that require bit operands for bits in the Core I/O Area ($0000 to $0FFF).
Page 83 Index and Data Registers (IR and DR) Section 3-12 of the hexadecimal address and adding the bit number as the rightmost digit. For example, the CIO bit 190000 is designated by $76CA where 76C is the rightmost three digits of the memory address (CIO word 1900 is $076C) and A is bit 10.
Page 84 Index and Data Registers (IR and DR) Section 3-12 would move the contents of CIO 1902 to CIO 1898; the third execution would move the contents of CIO 1904 to CIO 1897; etc. (030) Word Content Word Content IR0++ IR1– CIO 1900 08FC CIO 1899...
Page 85: Writing Programs
SECTION 4 Writing Programs This section explains the basic steps and concepts involved in writing a basic ladder diagram program. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution, along with a few other instructions of special interest in programming.
Page 86: Basic Procedure
Instruction Terminology Section 4-2 Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix E I/O Assignment Sheets and Appendix F Program Coding Sheet . 1, 2, 3...
Page 87: Basic Ladder Diagrams
Basic Ladder Diagrams Section 4-3 Basic Ladder Diagrams A ladder diagram consists of two vertical lines running down the sides with lines branching in between them. The vertical lines are called bus bars; the branch- ing lines, instruction lines or rungs. Along the instruction lines are placed conditions that lead to other instructions next to the right bus bar.
Page 88: Basic Mnemonic Code
Basic Ladder Diagrams Section 4-3 Execution Conditions In ladder diagram programming, the logical combination of ON and OFF condi- tions before an instruction determines the compound condition under which the instruction is executed. This condition, which is either ON or OFF, is called the execution condition for the instruction.
Page 89: Ladder Instructions
Basic Ladder Diagrams Section 4-3 Also, if an instruction requires only a single bit operand (with no definer), the bit operand is also placed on the same line as the instruction. The rest of the words required by an instruction contain the operands that specify what data is to be used.
Page 90 Basic Ladder Diagrams Section 4-3 LOAD and LOAD NOT The first condition that starts any logic block within a ladder diagram corre- sponds to a LOAD or LOAD NOT instruction. Each of these instructions is written on one line of mnemonic code. “Instruction” is used as a dummy instruction in the following examples and could be any of the right-hand instructions described lat- er in this manual.
Page 91: Output And Output Not
Basic Ladder Diagrams Section 4-3 The instruction at the right would have an ON execution condition when any one of the three conditions was ON, i.e., when CIO 00000 was OFF, when CIO 00100 was OFF, or when CIO 000200 was ON. OR and OR NOT instructions can be considered individually, each taking the logical OR between the execution condition produced by the preceding instruc- tions and the status of the OR instruction’s operand bit.
Page 92: Mnemonic Code
Mnemonic Code Section 4-4 In the above examples, CIO 000200 will be ON as long as CIO 000000 is ON and CIO 000201 will be ON as long as CIO 000001 is OFF. Here, CIO 000000 and CIO 000001 would be input bits and CIO 000200 and CIO 000201 output bits assigned to the Units controlled by the PC, i.e., the signals coming in through the input points assigned CIO 000000 and CIO 000001 are controlling the output points to which CIO 000200 and CIO 000201 are allocated.
Page 93 Mnemonic Code Section 4-4 AND LOAD Although simple in appearance, the diagram below requires an AND LOAD instruction. 0000 0000 Address Instruction Operands Instruction 00000 000000 0000 0000 00001 000001 00002 000002 00003 OR NOT 000003 00004 AND LD The two logic blocks are indicated by dotted lines. Studying this example shows that an ON execution condition will be produced when: either of the conditions in the left logic block is ON (i.e., when either CIO 000000 or CIO 000001 is ON) and either of the conditions in the right logic block is ON (i.e., when either...
Page 94 Mnemonic Code Section 4-4 OR LOAD The following diagram requires an OR LOAD instruction between the top logic block and the bottom logic block. An ON execution condition would be produced for the instruction at the right either when CIO 000000 is ON and CIO 000001 is OFF or when CIO 000002 and CIO 000003 are both ON.
Page 95 Mnemonic Code Section 4-4 Again, with the second method, a maximum of eight blocks can be combined. There is no limit to the number of blocks that can be combined with the first meth- The following diagram requires OR LOAD instructions to be converted to mne- monic code because three pairs of conditions in series lie in parallel to each oth- Address Instruction Operands 0000...
Page 96 Mnemonic Code Section 4-4 Although the following diagram is similar to the one above, block b in the diagram below cannot be coded without separating it into two blocks combined with OR LOAD. In this example, the three blocks have been coded first and then OR LOAD has been used to combine the last two blocks followed by AND LOAD to combine the execution condition produced by the OR LOAD with the execution condition of block a.
Page 97 Mnemonic Code Section 4-4 The following type of diagram can be coded easily if each block is coded in order: first top to bottom and then left to right. In the following diagram, blocks a and b would be combined using AND LOAD as shown above, and then block c would be coded and a second AND LOAD would be used to combined it with the execu- tion condition from the first AND LOAD.
Page 98 Mnemonic Code Section 4-4 The following diagram requires five blocks, which here are coded in order before using OR LOAD and AND LOAD to combine them starting from the last two blocks and working backward. The OR LOAD at program address 00008 com- bines blocks blocks d and e, the following AND LOAD combines the resulting execution condition with that of block c, etc.
Page 99: Branching Instruction Lines
Branching Instruction Lines Section 4-5 The first logic block instruction is used to combine the execution conditions re- sulting from blocks a and b, and the second one is to combine the execution condition of block c with the execution condition resulting from the normally closed condition assigned CIO 000003.
Page 100: Tr Bits
Branching Instruction Lines Section 4-5 this. In both diagrams, instruction 1 is executed before returning to the branching point and moving on to the branch line leading to instruction 2. Branching 0000 Address Instruction Operands point Instruction 1 00000 000000 0000 00001 Instruction 1...
Page 101 Branching Instruction Lines Section 4-5 In terms of actual instructions the above diagram would be as follows: The status of CIO 000000 is loaded (a LOAD instruction) to establish the initial execution condition. This execution condition is then output using an OUTPUT instruction to TR0 to store the execution condition at the branching point.
Page 102: Interlocks
Branching Instruction Lines Section 4-5 Note Although simplifying programs is always a concern, the order of execution of instructions is sometimes important. For example, a MOVE instruction may be required before the execution of a BINARY ADD instruction to place the proper data in the required operand word.
Page 103 Branching Instruction Lines Section 4-5 Diagram B can also be corrected with an interlock. Here, the conditions leading up to the branching point are placed on an instruction line for the INTERLOCK instruction, all of lines leading from the branching point are written as separate instruction lines, and another instruction line is added for the INTERLOCK CLEAR instruction.
Page 104: Jumps
Jumps Section 4-6 Jumps A specific section of a program can be skipped according to a designated execu- tion condition. Although this is similar to what happens when the execution condition for an INTERLOCK instruction is OFF, with jumps, the operands for all instructions maintain status.
Page 105: Controlling Bit Status
Controlling Bit Status Section 4-7 The same jump number cannot be used in more than one JUMP END instruc- tion. If you include more than one JUMP END instruction with the same jump number, all JUMP instructions with that jump number will jump to the first JUMP END instruction in the program with the same jump number.
Page 106: Differentiate Up And Differentiate Down
Controlling Bit Status Section 4-7 4-7-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN DIFFERENTIATE UP and DIFFERENTIATE DOWN instructions are used to turn the operand bit ON for one scan at a time. The DIFFERENTIATE UP instruc- tion turns ON the operand bit for one scan after the execution condition for it goes from OFF to ON;...
Page 107: Self-Maintaining Bits (Seal)
Controlling Bit Status Section 4-7 In the following example, CIO 000200 will be turned ON when CIO 000002 is ON and CIO 000003 is OFF. CIO 000200 will then remain ON until either CIO 000004 or CIO 000005 turns ON. With KEEP, as with all instructions requiring more than one instruction line, the instruction lines are coded first before the instruction that they control.
Page 108: Intermediate Instructions
Work Bits (Internal Relays) Section 4-9 Intermediate Instructions There are some instructions that can appear on instructions lines with conditions to help determine the execution conditions for other instructions. These instruc- tions are called intermediate instructions. Intermediate instructions cannot be placed next to the right bus bar, only between conditions or between a condition and a right-hand instruction.
Page 109 Work Bits (Internal Relays) Section 4-9 Reducing Complex Work bits can be used to simplify programming when a certain combination of Conditions conditions is repeatedly used in combination with other conditions. In the follow- ing example, CIO 000000, CIO 000001, CIO 000002, and CIO 000003 are com- bined in a logic block that stores the resulting execution condition as the status of CIO 024600.
Page 110: Programming Precautions
Programming Precautions Section 4-10 4-10 Programming Precautions The number of conditions that can be used in series or parallel is unlimited as long as the memory capacity of the PC is not exceeded. Therefore, use as many conditions as required to draw clear diagrams. Although very complicated dia- grams can be drawn with instruction lines, there must not be any conditions on lines running vertically between two other instruction lines.
Page 111: Program Execution
Using Version-2 CVM1 CPUs Section 4-12 When drawing ladder diagrams, it is important to keep in mind the number of instructions that will be required to input it. In diagram A, below, an OR LOAD instruction will be required to combine the top and bottom instruction lines. This can be avoided by redrawing as shown in diagram B so that no AND LOAD or OR LOAD instructions are required.
Page 112 Using Version-2 CVM1 CPUs Section 4-12 Most of these instructions are shown with a symbol and options. When the op- tions are not included, the instructions will handle unsigned one-word data. Symbol Option (data format) Option (data length) (Equal) S (signed) L (double) <...
Page 113 Using Version-2 CVM1 CPUs Section 4-12 With the input comparison instructions, however, the comparison results are di- rectly reflected as the input condition for the next instruction. This simplifies pro- gramming requirements by eliminating the need to use flags for that purpose. CMP(020) Example Execution A50006...
Page 114: Cmp And Cmpl
Using Version-2 CVM1 CPUs Section 4-12 4-12-2 CMP and CMPL CMP(020) and CMPL(021) are the same in the CV-series and CVM1-series as in the C-series in that they all output the comparison results to comparison flags. There are differences, however, in the way that are depicted in ladder diagrams. Comparison flag (020)
Page 115: Enhanced Math Instructions
Using Version-2 CVM1 CPUs Section 4-12 4-12-3 Enhanced Math Instructions The version-2 CVM1 CPUs provides symbol math instructions as an improve- ment over the earlier BCD and binary math instructions. The basic data format for these instructions is signed binary, although unsigned, BCD, and floating- point data options can be specified.
Page 116: Data Formats
Data Formats Section 4-13 Correspondence with The following table shows the correspondence between the symbol math instructions and the existing BCD and binary calculation instructions. Existing Instructions Existing instructions Version-2 instructions BCD ADD ADD(070) +BC (406) BCD SUBTRACT SUB(071) –BC(416) *B(424) BCD MULTIPLY MUL(072)
Page 117: Signed Binary Data
Data Formats Section 4-13 following example shows status 0000 “0011110000001110.” This would be represented as “3C0E” in hexadecimal. ON/OFF Digit Conversion to Decimal With unsigned binary data, the digits expressed in hexadecimal can be con- verted to decimal by multiplying the value of each digit by its respective factor. For example, the hexadecimal value “3C0E”...
Page 118 Data Formats Section 4-13 When the sign bit is ON, on the other hand, the number will be negative, and the method for converting to decimal will be different. Because the value is ex- pressed in 2’s complement, it must first be converted to a negative number and then the value of each digit can be multiplied by its respective factor.
Page 119 Data Formats Section 4-13 Signed Binary Data The following instructions carry out calculations on signed binary data. Calculations Operation Mnemonic Code Name Addition SIGNED BINARY ADD WITHOUT CARRY DOUBLE SIGNED BINARY ADD WITHOUT CARRY SIGNED BINARY ADD WITH CARRY DOUBLE SIGNED BINARY ADD WITH CARRY Subtraction –...
Page 120: Bcd Data
Data Formats Section 4-13 4-13-3 BCD Data With BCD data, 16-bit word data is expressed as 4-digit binary data (0000 to 9999) using only the hexadecimal numbers 0 to 9. If the data in any digit corre- sponds to the hexadecimal numbers A to F, an error will be generated. Digit In the following example, the bit status of CIO 0000 is shown as “0011100000000111.”...
Page 121: Instruction Set
SECTION 5 Instruction Set This section explains each instruction in the CV-series PC instruction sets and provides the ladder diagram symbols, data areas, and flags used with each. The instructions provided by the CV-series PC are described in following subsections by instruction group.
Page 122 5-14-10 DOUBLE SHIFT N-BITS RIGHT: NSRL(059) ......5-14-11 ARITHMETIC SHIFT LEFT: ASL(060) ....... 5-14-12 ARITHMETIC SHIFT RIGHT: ASR(061) .
Page 123 5-17-13 COLUMN TO LINE: LINE(115) ........5-17-14 LINE TO COLUMN: COLM(116) .
Page 124 5-22-1 INCREMENT BCD: INC(090) ........5-22-2 DECREMENT BCD: DEC(091) .
Page 125 5-31-1 INTERRUPT MASK: MSKS(153) ........5-31-2 CLEAR INTERRUPT: CLI(154) .
Page 126: Notation
Data Areas, Definer Values, and Flags Section 5-3 Notation In the remainder of this manual, instructions will be referred to by their mnemon- ics. For example, the OUTPUT instruction will be called OUT; the AND LOAD instruction, AND LD. If you’re not sure of the instruction a mnemonic is for, refer to Appendix B Programming Instructions .
Page 127 Data Areas, Definer Values, and Flags Section 5-3 Basic Ladder Symbol The ladder symbol shows how the instruction will appear in a program. The func- tion code (here, 210) is provided above the mnemonic (SA) and the operands are provided to the right (here, N and N ).
Page 128 Data Areas, Definer Values, and Flags Section 5-3 The Flags subsection lists flags that are affected by execution of an instruction. Flags These flags include the following Auxiliary Area flags. Abbreviation Name Instruction Execution Error Flag A50003 Carry Flag A50004 Greater Than Flag A50005 Equals Flag...
Page 129: Differentiated And Immediate Refresh Instructions
Differentiated and Immediate Refresh Instructions Section 5-4 When indirect DM data is designated as binary, the content of the *D or *E ad- Binary Indirect Addressing dress specifies the PC memory address, and thus can have any value between $0000 and $FFFF, as long as the instruction can be executed with the specified PC memory address.
Page 130 Differentiated and Immediate Refresh Instructions Section 5-4 The execution condition is always compared to the execution condition that ex- isted the last time the instruction was scanned, which may not be the previous cycle if an instruction is in a step in an SFC program, in a section of the program skipped by a jump, in a subroutine, etc.
Page 131: Coding Right-Hand Instructions
Coding Right-hand Instructions Section 5-5 Immediate refreshing and up or down differentiation can be combined in a single instruction. Immediate refresh instructions cannot be used for I/O points on Units mounted to Slave Racks in a SYSMAC BUS or SYSMAC BUS/2 Remote I/O System.
Page 132 Coding Right-hand Instructions Section 5-5 The following diagram and corresponding mnemonic code illustrates the points described above. Address Instruction Operands 00000 000000 00001 000001 0000 0000 (013) 00002 000002 DIFU 022500 00003 DIFU(013) 022500 0000 00004 000100 00005 AND NOT 000200 0001 0002...
Page 133: Ladder Diagram Instructions
Ladder Diagram Instructions Section 5-6 Ladder Diagram Instructions Ladder Diagram Instructions include Ladder Instructions and Logic Block Instructions. Ladder Instructions correspond to the conditions on the ladder diagram. Logic Block Instructions are used to relate more complex parts of the diagram that cannot be programmed with Ladder Instructions alone. 5-6-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT LOAD: LD Ladder Symbols...
Page 134 Ladder Diagram Instructions Section 5-6 OR: OR Ladder Symbols Operand Data Area B: Bit CIO, G, A, T, C, ST, TN Mnemonics ! j OR ! i OR j OR i OR ! OR OR NOT: OR NOT Ladder Symbols Operand Data Area B: Bit CIO, G, A, T, C, ST, TN...
Page 135: Condition On/Off: Up(018) And Down(019)
Ladder Diagram Instructions Section 5-6 5-6-2 CONDITION ON/OFF: UP(018) and DOWN(019) (CVM1 V2) Ladder Symbols (018) (019) DOWN Description UP(018) turns ON the execution condition for one cycle at the rising edge (OFF to ON) of the execution condition and then turns OFF the execution condition until the next time a rising edge is detected.
Page 136: Bit Test: Tst(350) And Tstn(351)
Ladder Diagram Instructions Section 5-6 5-6-3 BIT TEST: TST(350) and TSTN(351) (CVM1 V2) Ladder Symbol Operand Data Areas (350) S: Source word CIO, G, A, DM, DR, IR TST S N N: Bit number CIO, G, A, T, C, #, DM, DR, IR (351) TSTN S N Description...
Page 137: Not: Not(010)
Ladder Diagram Instructions Section 5-6 5-6-4 NOT: NOT(010) Ladder Symbol (010) Description NOT(010) reverses the execution condition. NOT(010) is an intermediate instruction that inverts the execution condition that precedes it. As an intermediate instruction, it cannot be placed at the end of an instruction line, only between conditions or between a condition and a right-hand instruction.
Page 138: Bit Control Instructions
Bit Control Instructions Section 5-7 Bit Control Instructions The instructions in this section are used to control bit status. These instructions are used to turn bits ON and OFF in different ways. 5-7-1 OUTPUT and OUTPUT NOT: OUT and OUT NOT OUTPUT: OUT Ladder Symbols Operand Data Area...
Page 139: Differentiate Up/Down: Difu(013) And Difd(014)
Bit Control Instructions Section 5-7 5-7-2 DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014) DIFFERENTIATE UP: DIFU(013) Ladder Symbol Operand Data Area (013) B: Bit CIO, G, A DIFU Variations !DIFU(013) DIFFERENTIATE DOWN: DIFD(014) Ladder Symbol Operand Data Area (014) B: Bit CIO, G, A DIFD Variations !DIFD(014)
Page 140 Bit Control Instructions Section 5-7 Example 1: Use when In diagram A, below, whenever MOVQ(037) is executed with an ON execution There’s No Differentiated condition it will move the contents of CIO 1200 to A001. If the execution condition Instruction remains ON, the content of A001 will be changed each cycle that the content of CIO 1200 changes.
Page 141: Set And Reset: Set(016) And Rset(017)
Bit Control Instructions Section 5-7 5-7-3 SET and RESET: SET(016) and RSET(017) SET: SET(016) Ladder Symbol Operand Data Area (016) B: Bit CIO, G, A Variations jSET(016) iSET(016) !SET(016) !jSET(016) !iSET(016) RESET: RSET(017) Ladder Symbol Operand Data Area (017) B: Bit CIO, G, A RSET Variations...
Page 142: Multiple Bit Set/Reset: Seta(047)/Rsta(048)
Bit Control Instructions Section 5-7 Precautions The status of operand bits for SET(016) and RSET (017) programmed between IL(002) and ILC(003) or JMP(004) and JME(005) will not change when the inter- lock or jump condition is met (i.e., when IL(002) or JMP(004) is executed with an OFF execution condition).
Page 143 Bit Control Instructions Section 5-7 Precautions must be between 0000 and 0015 and must be BCD. N must be BCD. Note: Refer to page 115 for general precautions on operand data areas. Flags ER (A50003): is not 0000 to 0015 BCD. is not BCD.
Page 144: Keep: Keep(011)
Bit Control Instructions Section 5-7 CIO 0005 Unchanged CIO 0006 Unchanged CIO 0007 CIO 0010 Unchanged CIO 0011 Unchanged CIO 0012 5-7-5 KEEP: KEEP(011) Ladder Symbol Operand Data Area (011) B: Bit CIO, G, A KEEP Variations !KEEP(011) Description KEEP(011) is used to maintain the status of the designated bit based on two execution conditions.
Page 145 Bit Control Instructions Section 5-7 KEEP(011) operates like the self-maintaining bit described in 4-7-4 Self-main- taining Bits (Seal) . The following two diagrams would function identically, though the one using KEEP(011) requires one less instruction to program and would maintain status even in an interlocked program section. Address Instruction Operands 0000 0000...
Page 146: Interlock And Interlock Clear: Il(002) And Ilc(003)
INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) Section 5-8 Example If a holding bit (default range: CIO 1200 to CIO 1499) is used, bit status will be retained even during a power interruption. KEEP(011) can thus be used to pro- gram bits that will maintain status after restarting the PC following a power inter- ruption.
Page 147 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) Section 5-8 If the execution condition for IL(002) is OFF, the interlocked section between IL(002) and ILC(003) will be treated as shown in the following table: Instruction Treatment OUT and OUT NOT Designated bit turned OFF. TIM, TIMH(015), and TIML(121) Reset.
Page 148: Jump And Jump End: Jmp(004) And Jme
JUMP and JUMP END: JMP(004) and JME(005) Section 5-9 Example The following diagram shows IL(002) being used twice with one ILC(003). 0000 (002) Address Instruction Operands 00000 000000 0000 00001 IL(002) 0511 #0015 1.5 s 00002 000001 0000 00003 T00511 (002) #0015 0000...
Page 149 JUMP and JUMP END: JMP(004) and JME(005) Section 5-9 Only one JME(005) instruction per jump number should be used in a program. If two or more JME(005) instructions with the same jump number are used in a program, program execution will skip to the JME(005) instruction at the lowest program address, even if it precedes the JMP(004) instruction.
Page 150: Conditional Jump: Cjp(221)/Cjpn(222)
CONDITIONAL JUMP: CJP(221)/CJPN(222) Section 5-10 5-10 CONDITIONAL JUMP: CJP(221)/CJPN(222) (CVM1 V2) Ladder Symbol Operand Data Areas (221) N: Jump number CIO, G, A, T, C, #, DM, DR, IR CJP N (222) CJP N Description CJP(221) operates in the reverse of JMP(004). When the execution condition turns ON, the program up until JME(005) is skipped.
Page 151: End: End(001)
Timer and Counter Instructions Section 5-13 5-11 END: END(001) Ladder Symbol (001) Description END(001) is required as the last instruction in any program, including all action and transition programs. No instruction written after END(001) will be executed. The END(001) instruction indicates the end of the relevant program for that cycle.
Page 152 Timer and Counter Instructions Section 5-13 Present values (PV) and Completion Flags for TIM and TIMH(015) timers are refreshed as shown in the following table. Instruction At execution At END(01) Interrupts PV refreshed and PV refreshed every Completion Flag turned refreshed 80 ms if cycle time ON if PV is 0000.
Page 153 Timer and Counter Instructions Section 5-13 Indirect Addressing Timer and counter numbers for TIM, TIMH(015), TTIM(120), CNT, CNTR(012), TIMW<013>, CNTW<014>, and TMHW<015> can be indirectly addressed us- ing the Index Registers by moving the PC memory address of the PV of the timer or counter number to the Index Register.
Page 154: Timer: Tim
Timer and Counter Instructions Section 5-13 The first MOV(030) instruction moves the PC memory address of the PV for tim- er T0000 ($1000) to IR0. The first MOVR(036) instruction moves the PC memory address of the Completion Flag for timer T0000 to IR1, and the second one moves the starting address into IR2.
Page 155 Timer and Counter Instructions Section 5-13 The following figure illustrates the relationship between the execution condition for TIM and the Completion Flag assigned to it. Execution condition Completion Flag Precautions SV must be between 000.0 and 999.9 and must be BCD. The decimal point is not entered.
Page 156 Timer and Counter Instructions Section 5-13 Example 1: The following example shows two timers, one set with a constant and one set via Basic Application input word 0005. Here, 000200 will be turned ON after 000000 goes ON and stays ON for at least 15 seconds. When 000000 goes OFF, the timer will be reset and 000200 will be turned OFF.
Page 157 Timer and Counter Instructions Section 5-13 In the following example, 000500 would be turned ON 5.0 seconds after 000000 goes ON and then turned OFF 3.0 seconds after 000000 goes OFF. It is neces- sary to use both 000500 and 000000 to determine the execution condition for T0002;...
Page 158: High-Speed Timer: Timh(015)
Timer and Counter Instructions Section 5-13 Example 5: Bits can be programmed to turn ON and OFF at regular intervals while a desig- Flicker Bits nated execution condition is ON by using TIM twice. One TIM functions to turn ON and OFF a specified bit, i.e., the Completion Flag of this TIM turns the speci- fied bit ON and OFF.
Page 159 Timer and Counter Instructions Section 5-13 Refer to 5-13-1 TIMER: TIM for operational details and examples. Except for the items mentioned above, all aspects of operation are the same. Precautions SV must be between 00.02 and 99.99 and must be BCD. The decimal point is not entered.
Page 160: Accumulative Timer: Ttim(120)
Timer and Counter Instructions Section 5-13 Example The following timing chart illustrates the operation of the first TIMH(015) in the following example. Timer input 000000 Completion Flag 000500 1.50 s When CIO 000001 is ON, the SV for the second TIMH(015) in the following ex- ample will be read from CIO 0020, allowing the SV of the timer to be control from an external device connected through CIO 0020.
Page 161 Timer and Counter Instructions Section 5-13 Precautions SV must be between 000.0 and 999.9 and must be BCD. The decimal point is not entered. Timer numbers are as shown in the following table. The “high-speed” timer num- bers should not be used for other timer instructions if they are required for TIMH(015).
Page 162: Long Timer: Timl(121)
Timer and Counter Instructions Section 5-13 CIO 000000 (input) CIO 000001 (reset) Completion Flag (T128) 5-13-4 LONG TIMER: TIML(121) Ladder Symbol Operand Data Areas (121) : Completion Flag CIO, G, A, DM TIML : PV word CIO, G, A, DM S: SV word CIO, G, A, T, C, #, DM Description...
Page 163: Multi-Output Timer: Mtim(122)
Timer and Counter Instructions Section 5-13 CIO 0101 and CIO 0100 will be decremented by –1 every 0.1 s. If the PV reaches 0000 0000, the Completion Flag (CIO 015000) will turn ON. If CIO 000000 turns OFF, the PV will again be set to the SV. 0000 Address Instruction Operands...
Page 164 Timer and Counter Instructions Section 5-13 If D is in the CIO, G, or A Area, the reset bit and pause bit can be controlled with SET(016) and RSET(017). If D is in the DM or EM Area, these bits can be con- trolled with the ANDW(130) and ORW(131) instructions.
Page 165: Counter: Cnt
Timer and Counter Instructions Section 5-13 Completion Flags CIO 0002 CIO 005000 CIO 0003 CIO 005001 CIO 0004 CIO 005002 CIO 0005 CIO 005003 CIO 0006 CIO 005004 CIO 0007 CIO 005005 CIO 0008 CIO 005006 CIO 0009 CIO 005007 5-13-6 COUNTER: CNT Ladder Symbol Operand Data Areas...
Page 166 Timer and Counter Instructions Section 5-13 Counter numbers are as shown in the following table. Each counter number can be used to define only one counter instruction unless the counters are never ac- tive simultaneously. Counter numbers CV500 or CVM1-CPU01-EV2 C0000 through C0511 CV1000, CV2000, or CVM1-CPU11/21-EV2 C0000 through C1023...
Page 167 Timer and Counter Instructions Section 5-13 CNT can be used in sequence as many times as required to produce counters capable of counting any desired values. 0000 0000 Address Instruction Operands 0001 #0100 0000 00000 000000 00001 000001 00002 LD NOT 000002 C0001 00003...
Page 168: Reversible Counter: Cntr(012)
Timer and Counter Instructions Section 5-13 Because in this example the SV for C0001 is 700, the Completion Flag for C0002 turns ON when 1 second x 700 times, or 11 minutes and 40 seconds, have ex- pired. This would result in 000202 being turned ON. 0000 A501 Address Instruction...
Page 169 Timer and Counter Instructions Section 5-13 When inputting the CNTR(012) instruction with mnemonics, first enter the incre- ment input (II), then the decrement input (DI), the reset input (R), and finally the CNTR(012) instruction. When entering with the ladder diagrams, first input the increment input (II), then the CNTR(012) instruction, the decrement input (DI), and finally the reset input (R).
Page 170: Reset Timer/Counter: Cnr(236)
Timer and Counter Instructions Section 5-13 The following diagram illustrates the operation of the Completion Flag (C0007) when the content of CIO 0001 (i.e., the SV) is 5000. 4999 5000 CIO 00003 0 5000 4999 CIO 00004 Completion Flag (C00007) 5-13-8 RESET TIMER/COUNTER: CNR(236) Ladder Symbol Operand Data Areas...
Page 171: Shift Instructions
Shift Instructions Section 5-14 5-14 Shift Instructions All of the Shift Instructions are used to shift data within or between words, but in differing amounts and directions. 5-14-1 SHIFT REGISTER: SFT(050) Ladder Symbol Operand Data Areas (050) St: Starting word CIO, G, A E: End word CIO, G, A...
Page 172 Shift Instructions Section 5-14 Example 1: The following example uses the 1-second clock pulse bit (A50102) so that the Basic Application execution condition produced by CIO 000005 is shifted into a 3-word register between CIO 0128 and CIO 0130 every second. Address Instruction Operands 0000...
Page 173 Shift Instructions Section 5-14 The program is set up so that a rotary encoder (000000) controls execution of SFT(050) through a DIFU(013), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor. Another sensor (000002) is used to detect faulty products in the chute so that the pusher output and bit 120003 of the shift register can be reset as required.
Page 174: Reversible Shift Register: Sftr(051)
Shift Instructions Section 5-14 5-14-2 REVERSIBLE SHIFT REGISTER: SFTR(051) Ladder Symbol Operand Data Areas (051) C: Control word CIO, G, A, DM, DR, IR SFTR St: Starting word CIO, G, A, DM Variations E: End word CIO, G, A, DM j SFTR(051) Description SFTR(051) is used to create a single- or multiple-word shift register that can shift...
Page 175: Asynchronous Shift Register: Asft(052)
Shift Instructions Section 5-14 Example In the following example, CIO bits 000005, 000006, 000007, and 000008 are used to control the bits of C used in j SFTR(051). The shift register is between words 0020 and 0021, and it is controlled through bit 000009. Address Instruction Operands...
Page 176 Shift Instructions Section 5-14 Content of C Function of ASFT(052) #4000 Shift non-zero data toward E #6000 Shift non-zero data toward St #8000 Reset all words to zero Precautions St must be less than or equal to E. St and E must be in the same data area. Note Refer to page 115 for general precautions on operand data areas.
Page 177: Word Shift: Wsft(053)
Shift Instructions Section 5-14 5-14-4 WORD SHIFT: WSFT(053) Ladder Symbol Operand Data Areas (053) S: Source word CIO, G, A, T, C, #, DM, DR, IR WSFT St: Starting word CIO, G, A, DM Variations E: End word CIO, G, A, DM j WSFT(053) Description When the execution condition is OFF, WSFT(053) is not executed.
Page 178: Shift N-Bit Data Left: Nsfl(054)
Shift Instructions Section 5-14 5-14-5 SHIFT N-BIT DATA LEFT: NSFL(054) (CVM1 V2) Ladder Symbol Operand Data Areas D: Beginning word for shift CIO, G, A NSFL D C N C: Beginning bit CIO, G, A, T, C, #, DM, DR, IR N: Shift data length CIO, G, A, T, C, #, DM, DR, IR Variations...
Page 179: Shift N-Bit Data Right: Nsfr(055)
Shift Instructions Section 5-14 D+1: Wd 0002 D: Wd 0001 N: 18 bits 0 0 0 1 1 After one execution 0 0 0 1 1 5-14-6 SHIFT N-BIT DATA RIGHT: NSFR(055) (CVM1 V2) Ladder Symbol Operand Data Areas NSFR D C N D: Beginning word for shift CIO, G, A C: Beginning bit CIO, G, A, T, C, #, DM, DR, IR...
Page 180: Shift N-Bits Left: Nasl(056)
Shift Instructions Section 5-14 Example When CIO 000000 is ON in the following example, the18 bits of data beginning from bit 03 of CIO 0001 are shifted to the right, one at a time. A “0” is entered for the beginning bit (CIO 000204) of the shift. The status of bit CIO 000103 is shifted to CY.
Page 181: Shift N-Bits Right: Nasr(057)
Shift Instructions Section 5-14 After the bits have been shifted, the status of the bits from which data was shifted (i.e., the number of bits shifted, beginning with the rightmost bit of the specified word) will be set to “0” or to the status of the LSB, depending on the control word setting.
Page 182: Double Shift N-Bits Left: Nsll(058)
Shift Instructions Section 5-14 After the bits have been shifted, the status of the bits from which data was shifted (i.e., the number of bits shifted, beginning with the leftmost bit of the specified word) will be set to “0” or to the status of the MSB, depending on the control word setting.
Page 183 Shift Instructions Section 5-14 After the bits have been shifted, the status of the bits from which data was shifted (i.e., the number of bits shifted, beginning with the rightmost bit of the specified word) will be set to “0” or to the status of the LSB, depending on the control word setting.
Page 184: Double Shift N-Bits Right: Nsrl(059)
Shift Instructions Section 5-14 5-14-10 DOUBLE SHIFT N-BITS RIGHT: NSRL(059) (CVM1 V2) Operand Data Areas Ladder Symbol NSRL D C D: Shift word address CIO, G, A, DM, C: Control word CIO, G, A, T, C, #, DM, Variations NSRL(059) Description When the execution condition is OFF, NSRL(059) is not executed.
Page 185: Arithmetic Shift Left: Asl(060)
Shift Instructions Section 5-14 Lost 0 entered. 5-14-11 ARITHMETIC SHIFT LEFT: ASL(060) Ladder Symbol Operand Data Area (060) Wd: Word CIO, G, A, DM, Variations j ASL(060) Description When the execution condition is OFF, ASL(060) is not executed. When the ex- ecution condition is ON, ASL(060) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Page 186: Arithmetic Shift Right: Asr(061)
Shift Instructions Section 5-14 5-14-12 ARITHMETIC SHIFT RIGHT: ASR(061) Ladder Symbol Operand Data Area (061) Wd: Word CIO, G, A, DM, DR, IR Variations j ASR(061) Description When the execution condition is OFF, ASR(061) is not executed. When the ex- ecution condition is ON, ASR(061) shifts a 0 into bit 15 of Wd, shifts the bits of Wd one bit to the right, and shifts the status of bit 00 into CY.
Page 187: Rotate Left: Rol(062)
Shift Instructions Section 5-14 5-14-13 ROTATE LEFT: ROL(062) Ladder Symbol Operand Data Area (062) Wd: Word CIO, G, A, DM, DR, IR Variations j ROL(062) Description When the execution condition is OFF, ROL(062) is not executed. When the ex- ecution condition is ON, ROL(062) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY.
Page 188: Rotate Right: Ror(063)
Shift Instructions Section 5-14 5-14-14 ROTATE RIGHT: ROR(063) Ladder Symbol Operand Data Area (063) Wd: Word CIO, G, A, DM, DR, IR Variations j ROR(063) Description When the execution condition is OFF, ROR(063) is not executed. When the ex- ecution condition is ON, ROR(063) shifts all Wd bits one bit to the right, shifting CY into bit 15 of Wd and shifting bit 00 of Wd into CY.
Page 189: Double Shift Left: Asll(064)
Shift Instructions Section 5-14 5-14-15 DOUBLE SHIFT LEFT: ASLL(064) Ladder Symbol Operand Data Area (064) Wd: Word CIO, G, A, DM ASLL Wd Variations j ASLL(064) Description When the execution condition is OFF, ASLL(064) is not executed. When the ex- ecution condition is ON, ASLL(064) shifts a 0 into bit 00 of Wd, all bits previously in Wd and Wd+1 are shifted to the left, and bit 15 of Wd+1 is shifted into CY.
Page 190: Double Shift Right: Asrl(065)
Shift Instructions Section 5-14 5-14-16 DOUBLE SHIFT RIGHT: ASRL(065) Ladder Symbol Operand Data Area (065) Wd: Word CIO, G, A, DM ASRL Wd Variations j ASRL(065) Description When the execution condition is OFF, ASRL(065) is not executed. When the ex- ecution condition is ON, ASRL(065) shifts a 0 into bit 15 of Wd+1, all bits pre- viously in Wd and Wd+1 are shifted to the right, and bit 00 of Wd is shifted into Wd+1...
Page 191: Double Rotate Left: Roll(066)
Shift Instructions Section 5-14 5-14-17 DOUBLE ROTATE LEFT: ROLL(066) Ladder Symbol Operand Data Area (066) Wd: Word CIO, G, A, DM ROLL Wd Variations j ROLL(066) Description When the execution condition is OFF, ROLL(066) is not executed. When the ex- ecution condition is ON, ROLL(066) shifts CY into bit 00 of Wd, all bits previously in Wd and Wd+1 are shifted to the left, and bit 15 of Wd+1 is shifted into CY.
Page 192: Rotate Left Without Carry: Rlnc(260)
Shift Instructions Section 5-14 (CVM1 V2) 5-14-18 ROTATE LEFT WITHOUT CARRY: RLNC(260) Ladder Symbol Operand Data Area (260) Wd: Word CIO, G, A, DM, DR, IR RLNC Wd Variations RNLC(260) Description When the execution condition is OFF, RLNC(260) is not executed. When the ex- ecution condition is ON, RLNC(260) shifts all Wd bits one bit to the left, shifting the status of bit 15 of Wd into both bit 00 and CY.
Page 193: Double Rotate Left Without Carry: Rlnl(262)
Shift Instructions Section 5-14 (CVM1 V2) 5-14-19 DOUBLE ROTATE LEFT WITHOUT CARRY: RLNL(262) Ladder Symbol Operand Data Area (262) Wd: Word CIO, G, A, DM RLNL Wd Variations RLNL(262) Description When the execution condition is OFF, RLNL(262) is not executed. When the ex- ecution condition is ON, RLNL(262) shifts all bits previously in Wd and Wd+1 to the left, and bit 15 of Wd+1 is shifted into both bit 00 of Wd and into CY.
Page 194: Double Rotate Right: Rorl(067)
Shift Instructions Section 5-14 5-14-20 DOUBLE ROTATE RIGHT: RORL(067) Ladder Symbol Operand Data Area (067) Wd: Word CIO, G, A, DM RORL Wd Variations j RORL(067) Description When the execution condition is OFF, RORL(067) is not executed. When the ex- ecution condition is ON, RORL(067) shifts CY into bit 15 of Wd+1, all bits pre- viously in Wd and Wd+1 are shifted to the right, and bit 00 of Wd is shifted into Wd+1...
Page 195: Rotate Right Without Carry: Rrnc(261)
Shift Instructions Section 5-14 (CVM1 V2) 5-14-21 ROTATE RIGHT WITHOUT CARRY: RRNC(261) Ladder Symbol Operand Data Area (261) Wd: Word CIO, G, A, DM, DR, IR RRNC Wd Variations RRNC(261) Description When the execution condition is OFF, RRNC(261) is not executed. When the execution condition is ON, RRNC(261) shifts all Wd bits one bit to the right, shift- ing the status of bit 00 into both bit 15 of Wd and into CY.
Page 196: Double Rotate Right W/O Carry: Rrnl(263)
Shift Instructions Section 5-14 (CVM1 V2) 5-14-22 DOUBLE ROTATE RIGHT W/O CARRY: RRNL(263) Ladder Symbol Operand Data Area (263) Wd: Word CIO, G, A, DM RRNL Wd Variations RRNL(263) Description When the execution condition is OFF, RRNL(263) is not executed. When the ex- ecution condition is ON, RRNL(263) shifts all bits previously in Wd and Wd+1 to the right, and bit 00 of Wd is shifted into both bit 15 of Wd+1 and into CY.
Page 197: One Digit Shift Left: Sld(068)
Shift Instructions Section 5-14 5-14-23 ONE DIGIT SHIFT LEFT: SLD(068) Ladder Symbol Operand Data Areas (068) St: Starting word CIO, G, A, DM E: End word CIO, G, A, DM Variations j SLD(068) Description When the execution condition is OFF, SLD(068) is not executed. When the ex- ecution condition is ON, SLD(068) shifts data between St and E (inclusive) by one digit (four bits) to the left.
Page 198: One Digit Shift Right: Srd(069)
Shift Instructions Section 5-14 5-14-24 ONE DIGIT SHIFT RIGHT: SRD(069) Ladder Symbol Operand Data Areas (069) St: Starting word CIO, G, A, DM E: End word CIO, G, A, DM Variations j SRD(069) Description When the execution condition is OFF, SRD(069) is not executed. When the ex- ecution condition is ON, SRD(069) shifts data between St and E (inclusive) by one digit (four bits) to the right.
Page 199: Data Movement Instructions
Data Movement Instructions Section 5-15 5-15 Data Movement Instructions Data Movement Instructions are used for moving data between different ad- dresses in data areas. These movements can be programmed to be within the same data area or between different data areas. Data movement is essential for utilizing all of the data areas of the PC.
Page 200: Move Not: Mvn(031)
Data Movement Instructions Section 5-15 5-15-2 MOVE NOT: MVN(031) Ladder Symbol Operand Data Areas (031) S: Source CIO, G, A, T, C, #, DM, DR, IR D: Destination CIO, G, A, T, C, DM, DR, IR Variations j MVN(031) Description When the execution condition is OFF, MVN(031) is not executed.
Page 201: Double Move: Movl(032)
Data Movement Instructions Section 5-15 5-15-3 DOUBLE MOVE: MOVL(032) Ladder Symbol Operand Data Areas (032) S: Source CIO, G, A, T, C, #, DM MOVL D: Destination CIO, G, A, T, C, DM Variations j MOVL(032) Description When the execution condition is OFF, MOVL(032) is not executed. When the ex- ecution condition is ON, MOVL(032) copies the content of S and S+1 to D and D+1.
Page 202: Double Move Not: Mvnl(033)
Data Movement Instructions Section 5-15 5-15-4 DOUBLE MOVE NOT: MVNL(033) Ladder Symbol Operand Data Areas (033) S: Source CIO, G, A, T, C, #, DM MVNL D: Destination CIO, G, A, T, C, DM Variations j MVNL(033) Description When the execution condition is OFF, MVNL(033) is not executed. When the ex- ecution condition is ON, MVNL(033) transfers the complement of the content of S and S+1 (specified words or eight-digit hexadecimal constant) to D and D+1, i.e., for each ON bit in S and S+1, the corresponding bit in D and D+1 is turned...
Page 203: Data Exchange: Xchg(034)
Data Movement Instructions Section 5-15 5-15-5 DATA EXCHANGE: XCHG(034) Ladder Symbol Operand Data Areas (034) Exchange word CIO, G, A, T, C, DM, DR, IR XCHG E Exchange word CIO, G, A, T, C, DM, DR, IR Variations j XCHG(034) Description When the execution condition is OFF, XCHG(034) is not executed.
Page 204: Double Data Exchange: Xcgl(035)
Data Movement Instructions Section 5-15 5-15-6 DOUBLE DATA EXCHANGE: XCGL(035) Ladder Symbol Operand Data Areas (035) Exchange word CIO, G, A, T, C, DM XCGL E Exchange word CIO, G, A, T, C, DM Variations j XCGL(035) Description When the execution condition is OFF, XCGL(035) is not executed. When the ex- ecution condition is ON, XCGL(035) exchanges the content of E and E +1 with...
Page 205: Move To Register: Movr(036)
Data Movement Instructions Section 5-15 5-15-7 MOVE TO REGISTER: MOVR(036) Ladder Symbol Operand Data Areas (036) S: Source CIO, G, A, TN, ST, T, C, DM MOVR D: Destination Variations j MOVR(036) Description When the execution condition is OFF, MOVR(036) is not executed. When the execution condition is ON, MOVR(036) copies the PC memory address of word or bit S to the index register designated in D.
Page 206: Move Quick: Movq(037)
Data Movement Instructions Section 5-15 5-15-8 MOVE QUICK: MOVQ(037) Ladder Symbol Operand Data Areas (037) S: Source CIO, G, A, T, C, # MOVQ D: Destination CIO, G, A, T, C Description When the execution condition is OFF, MOVQ(037) is not executed. When the execution condition is ON, MOVQ(037) copies the content of S to D at high speed.
Page 207: Multiple Bit Transfer: Xfrb(038)
Data Movement Instructions Section 5-15 5-15-9 MULTIPLE BIT TRANSFER: XFRB(038) (CVM1 V2) Ladder Symbol Operand Data Areas C: Control word CIO, G, A, T, C, #, DM, DR, IR XFRB C S D S: First source word CIO, G, A, T, C, DM D: First destination word CIO, G, A, DM Variations...
Page 208 Data Movement Instructions Section 5-15 Number of bits transferred 8 bits Example 2 When CIO 000000 is ON in the following example, 24 bits beginning with bit 12 of D00200 are transferred to D00500 (beginning with bit 08), as specified by the contents of D00100.
Page 209: Block Transfer: Xfer(040)
Data Movement Instructions Section 5-15 5-15-10 BLOCK TRANSFER: XFER(040) Ladder Symbol Operand Data Areas (040) N: Number of words CIO, G, A, T, C, #, DM, DR, IR XFER S: 1 source word CIO, G, A, T, C, DM Variations D: 1 destination word CIO, G, A, T, C, DM j XFER(040)
Page 210: Block Set: Bset(041)
Data Movement Instructions Section 5-15 5-15-11 BLOCK SET: BSET(041) Ladder Symbol Operand Data Areas (041) S: Source word CIO, G, A, T, C, #, DM, DR, IR BSET St: Starting word CIO, G, A, T, C, DM Variations E: End word CIO, G, A, T, C, DM j BSET(041) Description...
Page 211: Move Bit: Movb(042)
Data Movement Instructions Section 5-15 Example The following example shows how to use BSET(041) to change the PV of a timer depending on the status of CIO 000003 and CIO 000004. When CIO 000003 is ON, TIM 0010 will operate as a 50-second timer; when CIO 000004 is ON, TIM 0010 will operate as a 30-second timer.
Page 212 Data Movement Instructions Section 5-15 Example When CIO 000000 is ON in the following example, the content of bit 02 of the transfer source word (D00000) is copied to bit 12 of the transfer destination word (CIO 0005) as specified by the contents (1202) of control word (CIO 0035). 0000 Address Instruction...
Page 213: Move Digit: Movd(043)
Data Movement Instructions Section 5-15 5-15-13 MOVE DIGIT: MOVD(043) Ladder Symbol Operand Data Areas (043) S: Source word CIO, G, A, T, C, #, DM, DR, IR MOVD Di: Digit designator CIO, G, A, T, C, #, DM, DR, IR Variations D: Destination word CIO, G, A, T, C, DM, DR, IR...
Page 214: Single Word Distribute: Dist(044)
Data Movement Instructions Section 5-15 C : #0201 First digit in S: Number of digits: 1 digit First digit in D: S : D00000 D : D00003 5-15-14 SINGLE WORD DISTRIBUTE: DIST(044) Ladder Symbol Operand Data Areas (044) S: Source data CIO, G, A, T, C, #, DM, DR, IR DIST DBs: Destination base CIO, G, A, T, C, DM...
Page 215: Data Collect: Coll(045)
Data Movement Instructions Section 5-15 Before After execution execution CIO 0002 CIO 0002 CIO 0030 CIO 0030 D00410 D00410 5-15-15 DATA COLLECT: COLL(045) Ladder Symbol Operand Data Areas (045) SBs: Source base CIO, G, A, T, C, DM COLL SBs Of: Offset data CIO, G, A, T, C, #, DM, DR, IR Variations...
Page 216: Interbank Block Transfer: Bxfr(046)
Data Movement Instructions Section 5-15 5-15-16 INTERBANK BLOCK TRANSFER: BXFR(046) (CVM1 V2) Ladder Symbol Operand Data Areas (046) C: First control word CIO, G, A, T, C, DM BXFR C S D S: First source word CIO, G, A, T, C, DM D: First destination word CIO, G, A, T, C, DM Variations...
Page 217: Comparison Instructions
Comparison Instructions Section 5-16 Bank 5 Bank 1 5-16 Comparison Instructions Comparison Instructions are used for comparing data. All comparison instruc- tions affect only the comparison flags and/or results output words. They do not affect the content of the data being compared. Refer to page 99 for information explanations on comparison instructions sup- ported by version-2 CVM1 CPUs.
Page 218 Comparison Instructions Section 5-16 Placing other instructions between CMP(020) and the operation which ac- cesses the EQ, LE, and GR Flags may change the status of these flags. Be sure to access them before the desired status is changed. Note Refer to page 115 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD.
Page 219: Double Compare: Cmpl(021)
Comparison Instructions Section 5-16 The branching structure of this diagram is important in order to ensure that 000200, 000201, and 000202 are controlled properly as the timer counts down. Because all of the comparisons here use the timer’s PV as reference, the other operand for each CMP(020) must be in 4-digit BCD.
Page 220: Block Compare: Bcmp(022)
Comparison Instructions Section 5-16 Content of *DM word is not BCD when set for BCD. Flags ER (A50003): GR (A50005): Cp1+1 and Cp1 is greater than Cp2+1 and Cp2. EQ (A50006): Cp1+1 and Cp1 equals Cp2+1 and Cp2. LE (A50007): Cp1+1 and Cp1 is less than Cp2+1 and Cp2.
Page 221 Comparison Instructions Section 5-16 CB+24 CB+25 Bit 12 CB+26 CB+27 Bit 13 CB+28 CB+29 Bit 14 CB+30 CB+31 Bit 15 Precautions Each lower limit word in the comparison block must be less than or equal to the upper limit. CB cannot be one of the last 31 words in a data area because it designates the first of 32 words.
Page 222 Comparison Instructions Section 5-16 5-16-4 TABLE COMPARE: TCMP(023) Ladder Symbol Operand Data Areas (023) S: Source data CIO, G, A, T, C, #, DM, DR, IR TCMP TB: 1 table word CIO, G, A, T, C, DM Variations R: Result word CIO, G, A, T, C, DM, DR, IR j TCMP(023) Description...
Page 223: Multiple Compare: Mcmp(024)
Comparison Instructions Section 5-16 5-16-5 MULTIPLE COMPARE: MCMP(024) Ladder Symbol Operand Data Areas (024) table word CIO, G, A, T, C, DM MCMP TB table word CIO, G, A, T, C, DM Variations R: Result word CIO, G, A, DM, DR, IR j MCMP(024) Description When the execution condition is OFF, MCMP(024) is not executed.
Page 224: Equal: Equ(025)
Comparison Instructions Section 5-16 5-16-6 EQUAL: EQU(025) Ladder Symbol Operand Data Areas (025) compare word CIO, G, A, T, C, #, DM, DR, IR EQU Cp compare word CIO, G, A, T, C, #, DM, DR, IR Variations j EQU(025) Description When the execution condition is OFF, EQU(025) is not executed.
Page 225: Input Comparison Instructions (300 To 328)
Comparison Instructions Section 5-16 Example When CIO 000000 is ON in the following example, the content of CIO 0010 is compared to the content of D05000 and MOV(030) and INC(090) are executed only if the contents are the same. 0000 Address Instruction Operands (025)
Page 226 Comparison Instructions Section 5-16 Code Mnemonic Name Function TRUE WHEN S <> NOT EQUAL <>L DOUBLE NOT EQUAL <>S SIGNED NOT EQUAL <>SL DOUBLE SIGNED NOT EQUAL TRUE WHEN S < S < LESS THAN <L DOUBLE LESS THAN <S SIGNED LESS THAN <SL DOUBLE SIGNED LESS...
Page 227: Signed Binary Compare: Cps(026)
Comparison Instructions Section 5-16 When CIO 000001 is OFF, CIO 005001 is turned OFF. 0000 0050 Address Instruction Operands (310) 00000 000000 < D00100 D00200 0000 0050 00001 <(310) (312) D00100 <S D00110 D00210 D00200 00002 000001 00003 <S(312) D00110 D00210 Comparison : D00100...
Page 228: Double Signed Binary Compare: Cpsl(027)
Comparison Instructions Section 5-16 5-16-9 DOUBLE SIGNED BINARY COMPARE: CPSL(027) (CVM1 V2) Ladder Symbol Operand Data Areas : First comparison word 1 CIO, G, A, T, C, #, DM, CPSL S : First comparison word 2 CIO, G, A, T, C, #, DM, Description When the execution condition is OFF, CPSL(027) is not executed.
Page 229: Unsigned Compare: Cmp(028)
Comparison Instructions Section 5-16 5-16-10 UNSIGNED COMPARE: CMP(028) (CVM1 V2) Ladder Symbol Operand Data Areas : Comparison word 1 CIO, G, A, T, C, #, DM, DR, IR CMP S : Comparison word 2 CIO, G, A, T, C, #, DM, DR, IR Variations ! CMP(028) Description...
Page 230 Comparison Instructions Section 5-16 If the content of CIO 0011 and CIO 0010 is less than that of CIO 0009 and CIO 0008, then output CIO 002002 will turn ON. 0000 Address Instruction Operands (029) 00000 000000 CMPL 0010 0008 00001 CMPL(029) A50005...
Page 231: Conversion Instructions
Conversion Instructions Section 5-17 5-17 Conversion Instructions The Conversion Instructions convert word data that is in one format into another format and output the converted data to specified result word(s). All of these instructions change only the content of the words to which converted data is be- ing moved, i.e., the content of source words is the same before and after execu- tion of any of the conversion instructions.
Page 232: Binary-To-Bcd: Bcd(101)
Conversion Instructions Section 5-17 The bit contents of words D00010 and D00011 after execution are: D00010 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 D00011 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 5-17-2 BINARY-TO-BCD: BCD(101) Ladder Symbol Operand Data Areas...
Page 233: Double Bcd-To-Double Binary: Binl(102)
Conversion Instructions Section 5-17 Before After execution execution D00150 D00150 D00160 D00160 The bit contents of words D00150 and D00160 after execution are: D00150 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D00160 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 5-17-3 DOUBLE BCD-TO-DOUBLE BINARY: BINL(102)
Page 234: Double Binary-To-Double Bcd: Bcdl(103)
Conversion Instructions Section 5-17 S+1: CIO 0011 S: CIO 0010 200050=3X16 +13X16 +7X16 +2X16 R+1: D00201 R: D00200 5-17-4 DOUBLE BINARY-TO-DOUBLE BCD: BCDL(103) Ladder Symbol Operand Data Areas (103) S: Source word CIO, G, A, T, C, DM BCDL R: Result word CIO, G, A, DM Variations j BCDL(103)
Page 235: 2'S Complement: Neg(104)
Conversion Instructions Section 5-17 S+1: CIO 0011 S: CIO 0010 2X16 +13X16 +3X16 +2X16 +10=2961930 R+1: D00101 R: D00100 5-17-5 2’S COMPLEMENT: NEG(104) Ladder Symbol Operand Data Areas (104) S: Source word CIO, G, A, T, C, #, DM, DR, IR R: Result word CIO, G, A, DM, DR, IR Variations...
Page 236: Double 2'S Complement: Negl(105)
Conversion Instructions Section 5-17 5-17-6 DOUBLE 2’S COMPLEMENT: NEGL(105) Ladder Symbol Operand Data Areas (105) S: 1 source word CIO, G, A, T, C, #, DM NEGL R: 1 result word CIO, G, A, DM Variations j NEGL(105) Description When the execution condition is OFF, NEGL(105) is not executed. When the execution condition is ON, NEGL(105) converts the 8-digit hexadecimal content of the source words (S and S+1) to its 2’s complement and outputs the result to the result words (R and R+1).
Page 237: Sign: Sign(106)
Conversion Instructions Section 5-17 5-17-7 SIGN: SIGN(106) Ladder Symbol Operand Data Areas (106) S: Source word CIO, G, A, T, C, #, DM, DR, IR SIGN R: 1 result word CIO, G, A, DM Variations j SIGN(106) Description When the execution condition is OFF, SIGN(106) is not executed. When the execution condition is ON, SIGN(106) copies the 4-digit signed binary source word (S) to R, extracts the sign from bit 15 of S, and outputs the result to R+1.
Page 238: Data Decoder: Mlpx(110)
Conversion Instructions Section 5-17 5-17-8 DATA DECODER: MLPX(110) Ladder Symbol Operand Data Areas (110) S: Source word CIO, G, A, T, C, DM, DR, IR MLPX Di: Digit designator CIO, G, A, T, C, #, DM, DR, IR Variations R: 1 result word CIO, G, A, DM, j MLPX(110)
Page 239 Conversion Instructions Section 5-17 Digit Designator The digits of Di are set as shown below. Digit number: 3 2 1 0 Specifies the first digit to be converted 4-to-16: 0 to 3 8-to-256: 0 or 1 Number of digits to be converted 4-to-16: 0 to 3 (1 to 4 digits) 8-to-256: 0 or 1 (1 or 2 digits) Process...
Page 240: Data Encoder: Dmpx(111)
Conversion Instructions Section 5-17 Example When CIO 000000 is ON in the following example, three digits of data from CIO 0020 is converted to bit positions and the corresponding bits in three con- secutive words starting with D 00100 are turned ON to indicate the position of the ON bits.
Page 241 Conversion Instructions Section 5-17 For 16-bit conversion, DMPX(111) determines the position of the highest ON bit in SB, encodes it into one-digit hexadecimal value corresponding to the bit num- ber of the highest ON bit, then transfers the hexadecimal value to the specified 4-bit digit in R.
Page 242 Conversion Instructions Section 5-17 Digit Designator The digits of Di are set as shown below. Digit number: 3 2 1 0 Specifies the first digit to receive converted data 16-to-4: 0 to 3 256-to-8: 0 or 1 Number of digits to be converted 16-to-4: 0 to 3 (1 to 4 digits) 256-to-8: 0 or 1 (1 or 2 digits) Encoding bit (See note.)
Page 243: 7-Segment Decoder: Sdec(112)
Conversion Instructions Section 5-17 Example When CIO 000000 is ON in the following example, the bit positions of the highest ON bits in CIO 0010 and 0011 are written to the first two digits of CIO 0020 and the bit positions of the highest ON bits in CIO 0015 and CIO 0016 are written to the last two digits of 0020.
Page 244 Conversion Instructions Section 5-17 Digit Designator The digits of Di are set as shown below. Digit number: 3 2 1 0 Specifies the first digit to receive converted data (0 to 3). Number of digits to be converted (0 to 3) 0: 1 digit 1: 2 digits 2: 3 digits...
Page 245 Conversion Instructions Section 5-17 The table underneath shows the original data and converted code for all hexa- decimal digits. Bit 00 1: Second digit 0: One digit Bit 07 Bits 00 through 07 Not used. Original data Converted code (segments) Display Digit Bits...
Page 246: Ascii Convert: Asc(113)
Conversion Instructions Section 5-17 5-17-11 ASCII CONVERT: ASC(113) Ladder Symbol Operand Data Areas (113) S: Source word CIO, G, A, T, C, DM, DR, IR Di: Digit designator CIO, G, A, T, C, #, DM, DR, IR Variations D: 1 destination word CIO, G, A, DM j ASC(113) Description...
Page 247 Conversion Instructions Section 5-17 Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below. Di: 0011 Di: 0030 1st half 1st half 2nd half 2nd half 1st half 2nd half Di: 0112 Di: 0130 1st half 1st half...
Page 248: Bit Counter: Bcnt(114)
Conversion Instructions Section 5-17 Di : #0000 0 0 0 0 Convert from digit 0. Convert 1 digit. Output to leftmost bits. No parity. S: D00010 D: CIO 0001 000100 000101 000102 000103 000104 000105 000106 000107 000108 000109 000110 000111 000112 000113...
Page 249: Column To Line: Line(115)
Conversion Instructions Section 5-17 Example When CIO 000007 is ON in the following example, all ON bits in D00030 and D00031 are counted and the results is placed in D00040. 0000 Address Instruction Operands (114) BCNT #0002 D00030 D00040 00000 000007 00001 BCNT(114)
Page 250: Line To Column: Colm(116)
Conversion Instructions Section 5-17 Content of *DM word is not BCD when set for BCD. Flags ER (A50003): The bit designator Bi is not BCD, or it is specifying a non-ex- istent bit (i.e., bit specification must be between 00 and 15). EQ (A50006): Content of D is 0 after execution Example...
Page 251: Ascii To Hex: Hex(117)
Conversion Instructions Section 5-17 Example When CIO 000000 is ON in the following example, the status of bits 00 to 15 in D00005 are copied consecutively to bits number 08 of D00010 through D00025, with the status of bit 00 being transferred to bit 08 of D00010. 0000 Address Instruction Operands...
Page 252 Conversion Instructions Section 5-17 Digit Designator Examples The following examples show the digit designators (Di) used to make various multiple-word conversions. Example 1 Di Word Contents Word S+1 Word S Leftmost 8 bits Rightmost 8 bits Leftmost 8 bits Rightmost 8 bits Digit 3 Digit 2 Digit 1 Digit 0...
Page 253 Conversion Instructions Section 5-17 2: Odd The data (8 bits) can only be converted when the number of “1” bits is odd. If the number is even, the Error Flag will turn ON and the data will not be converted. Example “A”...
Page 254: Signed Bcd-To-Binary: Bins(275)
Conversion Instructions Section 5-17 Parity bits: Even 1 1 0 0 0 0 1 1 1 0 1 1 1 0 0 0 First ASCII data to be converted: Rightmost 8 bits Converted to binary data First digit to receive converted data: 1 : Not changed.
Page 255 Conversion Instructions Section 5-17 When C = 0002 (Input Data Range: –999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative (–) A to E: Error When C = 0003 (Input Data Range: –1999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (–1)
Page 256: Signed Binary-To-Bcd: Bcds(276)
Conversion Instructions Section 5-17 Example 2 When CIO 000001 is ON in the following example, first the signed BCD data for- mat and range in D00300 are checked against data control word “0003” (first operand). If the check is okay, the signed BCD data in D00300 is converted to binary and output to D00400.
Page 257 Conversion Instructions Section 5-17 When C = 0002 (Output Data Range: –999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative (–) When C = 0003 (Output Data Range: –1999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (–1)
Page 258: Double Signed Bcd-To-Binary: Bisl(277)
Conversion Instructions Section 5-17 S: D00300 Signed binary data F A A 7 D: D00400 Signed BCD data A 3 6 9 (–1369) 5-17-18 DOUBLE SIGNED BCD-TO-BINARY: BISL(277) (CVM1 V2) Ladder Symbol Operand Data Areas (277) C: Control word CIO, G, A, T, C, #, DM, BISL C S D S: 1st source word CIO, G, A, T, C, DM,...
Page 259 Conversion Instructions Section 5-17 When C = 0003 (Input Data Range: –1999 9999 to 9999 9999 BCD) 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD A: Negative (-1) F: Negative (–) B to E: Error First the signed BCD data format and range in words S+1 and S are checked against the data control word (C).
Page 260: Double Signed Binary-To-Bcd: Bdsl(278)
Conversion Instructions Section 5-17 5-17-19 DOUBLE SIGNED BINARY-TO-BCD: BDSL(278) (CVM1 V2) Ladder Symbol Operand Data Areas (278) C: Control word CIO, G, A, T, C, #, DM, BDSL C S D S: 1st source word CIO, G, A, T, C, DM, Variations D: 1st destination word CIO, G, A, DM,...
Page 261: Bcd Calculation Instructions
BCD Calculation Instructions Section 5-18 First the signed BCD data format and range in words S+1 and S are checked against the data control word (C). If the check is okay, the signed BCD data in words S+1 and S is converted to binary and output to the designated words D+1 and D.
Page 262: Set Carry: Stc(078)
BCD Calculation Instructions Section 5-18 5-18-1 SET CARRY: STC(078) Ladder Symbol Variations j STC(078) (078) When the execution condition is OFF, STC(078) is not executed. When the execution condition is ON, STC(078) turns ON CY (A50004). 5-18-2 CLEAR CARRY: CLC(079) Ladder Symbol Variations j CLC(078)
Page 263: Bcd Subtract: Sub(071)
BCD Calculation Instructions Section 5-18 Example When CIO 000000 is ON in the following example, CY is cleared by CLC(079), the content of CIO 0200 is added to the contents of CIO 0100 and the status of CY, the results is placed in D00100, and then either all zeros or 0001 is moved into D00101 depending on the status of CY (A50004).
Page 264 BCD Calculation Instructions Section 5-18 Note Be sure to clear the carry flag with CLC(079) before executing SUB(071) if its previous status is not required, and check the status of CY after doing a subtrac- tion with SUB(071). If CY is ON as a result of executing SUB(071) (i.e., if the re- sult is negative), the result is output as the 10’s complement of the true answer.
Page 265: Bcd Multiply: Mul(072)
BCD Calculation Instructions Section 5-18 Second Subtraction 0000 CIO 0200 –7577 –0 CIO 0200 2423 (0000 + (10000 – 7577)) (negative result) In the above case, the program would turn ON CIO 002100 to indicate that the value held in CIO 0200 is negative. 5-18-5 BCD MULTIPLY: MUL(072) Ladder Symbol Operand Data Areas...
Page 266: Bcd Divide: Div(073)
BCD Calculation Instructions Section 5-18 Example When CIO 000000 is ON in the following example, the contents of CIO 0013 and D00005 are multiplied and the results is placed in CIO 1207 and CIO 1208. Example data and calculations are shown below the program. 0000 Address Instruction Operands...
Page 267: Double Bcd Add: Addl(074)
BCD Calculation Instructions Section 5-18 Example When CIO 000000 is ON in the following example, the content of CIO 0020 is divided by the content of CIO 1209 and the results is placed in D00017 and D00018. Example data and calculations are shown below the program. 0000 Address Instruction Operands...
Page 268: Double Bcd Subtract: Subl(075)
BCD Calculation Instructions Section 5-18 The carry from the second addition is placed in D02003 by using another ADD(070) with two all-zero constants. 00000 Address Instruction Operands (079) 00000 000003 (074) 00001 CLC(079) ADDL 0020 D00010 D02000 00002 ADDL(074) (070) 0022 D00012 D02002...
Page 269: Double Bcd Multiply: Mull(076)
BCD Calculation Instructions Section 5-18 Example The following example works much like that for single-word subtraction. In this example, however, the 8-digit number in CIO 0121 and CIO 0120 is subtracted from the 8-digit number in CIO 0201 and CIO 0200 when CIO 000003 is ON, and the result is output to D00101 and D00100.
Page 270: Double Bcd Divide: Divl(077)
BCD Calculation Instructions Section 5-18 Note Refer to page 115 for general precautions on operand data areas. Flags ER (A50003): Content of Md, Md+1, Mr, or Mr+1 is not BCD. Content of *DM word is not BCD when set for BCD. EQ (A50006): The result is 0.
Page 271 BCD Calculation Instructions Section 5-18 Flags ER (A50003): Dr and Dr+1 contain 0. Content of Dd, Dd+1, Dr or Dr+1 is not BCD. The content of a *DM word is not BCD when set for BCD. CY (A50004): There is a carry in the result. EQ (A50006): The result is 0.
Page 272 BCD Calculation Instructions Section 5-18 0000 Address Instruction Operands (041) jBSET #0000 D00101 D00102 00000 000000 "BSET(041) 00001 (030) jMOV #000 #0000 D00000 D00101 (020) D00102 D00000 #0100 "MOV(030) 00002 A500 #0000 (090) D00000 D00000 00003 CMP(020) (030) MOV *D00000 0200 D00000 #0100...
Page 273: Binary Calculation Instructions
Binary Calculation Instructions Section 5-19 5-19 Binary Calculation Instructions The Binary Calculation Instructions all perform arithmetic operations on binary (hexadecimal) data. The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the cal- culation, and to use the result placed in CY, if required, before it is changed by the execution of any other instruction.
Page 274: Binary Subtract: Sbb(081)
Binary Calculation Instructions Section 5-19 Examples The following example shows a four-digit addition with CY used to place either 0000 or 0001 into R+1 to ensure that any carry is preserved. Address Instruction Operands 0000 (079) 00000 000000 00001 (080) 00002 CLC(079) 0010...
Page 275 Binary Calculation Instructions Section 5-19 Note With version-2 CVM1 CPUs, mathematics instructions can use symbols. The instructions corresponding to SUB(081) and SUBL(085) are –C(412) and – CL(413). In addition, Overflow (A50009) and Underflow (A50010) Flags are added. Precautions Refer to page 115 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD.
Page 276: Binary Multiply: Mlb(082)
Binary Calculation Instructions Section 5-19 In the following example, 20F55A10 – B8A360E3 = 97AE06D3. In the rightmost four-digit subtraction, Su is less than Mi, so CY (A50004) becomes 1, and the result of the leftmost four-digit subtraction is decremented by 1. In the final cal- culations, 0000 –...
Page 277: Binary Divide: Dvb(083)
Binary Calculation Instructions Section 5-19 Note With version-2 CVM1 CPUs, mathematics instructions can use symbols. The instructions corresponding to MLB(082) and MLBL(086) are U(422) and UL(423). Precautions Refer to page 115 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006):...
Page 278: Double Binary Add: Adbl(084)
Binary Calculation Instructions Section 5-19 Note Refer to page 115 for general precautions on operand data areas. Flags ER (A50003): Dr contains 0. Content of *DM word is not BCD when set for BCD. EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R.
Page 279 Binary Calculation Instructions Section 5-19 Precautions Refer to page 115 for general precautions on operand data areas. Content of *DM word is not BCD when set for BCD. Flags ER (A50003): CY (A50004): The result is greater than FFFF FFFF. EQ (A50006): The result is 0.
Page 280: Double Binary Subtract: Sbbl(085)
Binary Calculation Instructions Section 5-19 5-19-6 DOUBLE BINARY SUBTRACT: SBBL(085) Ladder Symbol Operand Data Areas (085) Mi: 1 minuend word CIO, G, A, T, C, #, DM SBBL Su: 1 subtrahend wordCIO, G, A, T, C, #, DM Variations R: 1 result word CIO, G, A, DM j SBBL(085)
Page 281: Double Binary Multiply: Mlbl(086)
Binary Calculation Instructions Section 5-19 97A071CA – 0F3B52D8 = 88651DF2 Mi : D00100 Mi + 1 : D00101 Su +1 : CIO 0201 Su : CIO 0200 – CY (Cleared with CYC(079)) D + 1 : DD00501 D : D00500 CY (No carry) N (Leftmost bit is ON) 5-19-7 DOUBLE BINARY MULTIPLY: MLBL(086)
Page 282: Double Binary Divide: Dvbl(087)
Binary Calculation Instructions Section 5-19 D00011 D00010 0 9 5 A F 8 A A 0 0 0 0 0 0 F F D00023 D00022 D00021 D00020 0 0 0 0 0 0 0 9 5 1 9 D B 1 5 6 5-19-8 DOUBLE BINARY DIVIDE: DVBL(087) Ladder Symbol Operand Data Areas...
Page 283 Binary Calculation Instructions Section 5-19 Dd+1: CIO 0101 Dd: CIO 0100 0 0 A B C D E F Dr+1: D00501 Dr : D00500 0 0 0 0 0 1 0 0 R+3: D00203 R+2: D00202 R+1: D00201 R: D00200 0 0 0 0 0 0 E F 0 0 0 0...
Page 284: Symbol Math Instructions
Symbol Math Instructions Section 5-20 5-20 Symbol Math Instructions The Symbol Math Instructions perform arithmetic operations on BCD or binary data. 5-20-1 Binary Addition: +(400)/+L(401)/+C(402)/+CL(403) (CVM1 V2) SIGNED BINARY ADD WITHOUT CARRY: +(400) Ladder Symbol Operand Data Areas (400) Au: Augend word CIO, G, A, T, C, #, DM, DR, IR Ad: Addend word CIO, G, A, T, C, #, DM, DR, IR...
Page 285 Symbol Math Instructions Section 5-20 DOUBLE SIGNED BINARY ADD WITHOUT CARRY When the execution condition is OFF, +L(401) is not executed. When the execu- tion condition is ON, +L(401) adds the 8-digit contents of Au+1 and Au and the 8-digit contents of Ad+1 and Ad, and places the result in R and R + 1. CY will be set if the result is greater than FFFF FFFF.
Page 286: Bcd Addition: +B(404)/ +Bl(405)/+Bc(406)/+Bcl(407)
Symbol Math Instructions Section 5-20 When Au and Ag are both positive numbers and the addition result is negative, the Overflow Flag (A50009) turns ON. When Au and Ag are both negative num- bers and the addition result is positive, the Underflow Flag (A50010) turns ON. If a addition result in a carry, the Carry Flag turns ON.
Page 287 Symbol Math Instructions Section 5-20 Description BCD ADD WITHOUT CARRY When the execution condition is OFF, +B(404) is not executed. When the execu- tion condition is ON, +B(404) adds the contents of Au and Ad and places the re- sult in R. CY will be set if the result is greater than 9999. DOUBLE BCD ADD WITHOUT CARRY When the execution condition is OFF, +BL(405) is not executed.
Page 288: Binary Subtraction: -(410)/ -L(411)/-C(412)/-Cl(413)
Symbol Math Instructions Section 5-20 Example +BL Operation When CIO 000000 is ON in the following example, the contents of D00101 and D00100 are added to the content of D00111 and D00110, and the result is output in eight-digit BCD to D00121 and D00120. +BCL Operation When CIO 000001 is ON in the following example, the contents of D00201 and D00200 are added to the content of D00211 and D00210, and the result includ-...
Page 289 Symbol Math Instructions Section 5-20 DOUBLE SIGNED BINARY SUBTRACT WITH CARRY: –CL(413) Ladder Symbol Operand Data Areas (413) Mi: Minuend word CIO, G, A, T, C, #, DM, –CL Su: Subtrahend word CIO, G, A, T, C, #, DM, Variations R: Result word CIO, G, A, DM, j –CL(413)
Page 290 Symbol Math Instructions Section 5-20 Flags ER (A50003): The content of a*DM word is not BCD when set for BCD. CY (A50004): The subtraction resulted in a borrow. EQ(A50006) The contents of word R (or word R and R+1 for “double” instructions) after the subtraction is all zeros N (A50008) The leftmost bit (MSB) of word R (or word R+1 for “double”...
Page 291 Symbol Math Instructions Section 5-20 Programming Example 1 –L Operation When CIO 000000 is ON in the following example, the content of D00111 and D00110 is subtracted from the content of D00101 and D00100, and the result is output in eight-digit binary to D00121 and D00120. CY is set if the subtraction resulted in a borrow.
Page 292 Symbol Math Instructions Section 5-20 Subtraction at 1 Mi+1: CIO 0201 Mi: CIO 0200 2 0 F 5 Su+1: CIO 0121 Su: CIO 0120 – R+1: D00101 R+1: D00100 F 9 2 D The Carry Flag (A50004) is ON, so the result is subtracted from 0000 0000 to obtain the actual result.
Page 293: Bcd Subtraction: -B(414)/ -Bl(415)/-Bc(416)/-Bcl(417)
Symbol Math Instructions Section 5-20 5-20-4 BCD Subtraction: –B(414)/ –BL(415)/–BC(416)/–BCL(417) (CVM1 V2) BCD SUBTRACT WITHOUT CARRY: –B(414) Ladder Symbol Operand Data Areas (414) Mi: Minuend word CIO, G, A, T, C, #, DM, DR, IR –B Su: Subtrahend word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR...
Page 294 Symbol Math Instructions Section 5-20 DOUBLE BCD SUBTRACT WITHOUT CARRY When the execution condition is OFF, –BL(415) is not executed. When the execution condition is ON, –BL(415) subtracts the 8-digit BCD content of Su and Su+1 from the 8-digit BCD content in Mi and Mi+1, and places the result in R and R+1.
Page 295 Symbol Math Instructions Section 5-20 –BCL Operation When CIO 000001 is ON in the following example, the content of D00211 and D00210 are subtracted from the content of D00201 and D00200, and the result including the carry is output in eight-digit BCD to D00221 and D00220. CY is set if the result is negative Address Instruction Operands...
Page 296 Symbol Math Instructions Section 5-20 Subtraction at 1 Mi+1: CIO 0201 Mi: CIO 0200 0 9 5 8 Su+1: CIO 0121 Su: CIO 0120 – 09583960 + (100000000 – 17072641) R+1: D00101 R+1: D00100 9 2 2 5 1 1 3 1 9 The Carry Flag (A50004) is ON, so the result is subtracted from 0000 0000.
Page 297: Binary Multiplication: *(420)/ *L(421)/*U(422)/*Ul(423)
Symbol Math Instructions Section 5-20 5-20-5 Binary Multiplication: *(420)/ *L(421)/*U(422)/*UL(423) (CVM1 V2) SIGNED BINARY MULTIPLY: *(420) Ladder Symbol Operand Data Areas (420) Md: Multiplicand word CIO, G, A, T, C, #, DM, DR, IR Mr: Multiplier word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM...
Page 298 Symbol Math Instructions Section 5-20 DOUBLE SIGNED BINARY MULTIPLY When the execution condition is OFF, *L(421) is not executed. When the execu- tion condition is ON, *L(421) multiplies the signed 8-digit content of Md and Md+1 by the signed content of Mr and Mr+1, and places the result in R to R+3. Md + 1 Mr + 1 R + 3...
Page 299: Bcd Multiplication: *B(424)/ *Bl(425)
Symbol Math Instructions Section 5-20 *UL Operation When CIO 000001 is ON in the following example, the content of D00201 and D00200 are multiplied by the content of D00211 and D00210, in eight-digit binary without sign, and the result is output to D00223 through D00220. Address Instruction Operands 0000...
Page 300 Symbol Math Instructions Section 5-20 DOUBLE BCD MULTIPLY When the execution condition is OFF, *BL(425) is not executed. When the execution condition is ON, *BL(425) multiplies the 8-digit BCD content of Md and Md+1 by the BCD content of Mr and Mr+1, and places the result in R to R+3. Md + 1 Mr + 1 R + 3...
Page 301: Binary Division: /(430)/ /L(431)//U(432)//Ul(433)
Symbol Math Instructions Section 5-20 5-20-7 Binary Division: /(430)/ /L(431)//U(432)//UL(433) (CVM1 V2) SIGNED BINARY DIVIDE: /(430) Ladder Symbol Operand Data Areas (430) Dd: Dividend word CIO, G, A, T, C, #, DM, DR, IR Dr: Divisor word CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM...
Page 302 Symbol Math Instructions Section 5-20 DOUBLE SIGNED BINARY DIVIDE When the execution condition is OFF, /L(431) is not executed. When the execu- tion condition is ON, /L(431) divides the signed 8-digit content of Dd and D+1 by the signed content of Dr and Dr+1 and the result is placed in R to R+3: the quo- tient in R and R+1, and the remainder in R+2 and R+3.
Page 303: Bcd Division: /B(434)/ /Bl(435)
Symbol Math Instructions Section 5-20 /UL Operation When CIO 000001 is ON in the following example, the unsigned content of D00201 and D00200 is divided by the unsigned content of D00211 and D00210, in eight-digit binary. When the result is obtained, the quotient is output to D00221 and D00220, and the remainder is output to D00223 and D00222.
Page 304 Symbol Math Instructions Section 5-20 DOUBLE BCD DIVIDE When the execution condition is OFF, /BL(435) is not executed. When the execution condition is ON, the BCD 8-digit content of Dd and D+1 is divided by the BCD content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, and the remainder in R+2 and R+3.
Page 305: Floating-Point Math Instructions
Floating-point Math Instructions Section 5-21 5-21 Floating-point Math Instructions The Floating-point Math Instructions convert data and perform floating-point arithmetic operations. Version-2 CVM1 CPUs support the following instructions. Code Mnemonic Name FIX (*) FLOATING TO 16-BIT FIXL (*) FLOATING TO 32-BIT FLT (*) 16-BIT TO FLOATING FLTL (*)
Page 306 Floating-point Math Instructions Section 5-21 Floating-point Data The following data can be expressed by floating-point data: –R x value x –1.175494 x 10 –38 –3.402823 x 10 x value x 3.402823 x 10 –38 1.175494 x 10 Not a number (NaN) –38 –38 –1.175494 x 10...
Page 307 Floating-point Math Instructions Section 5-21 0000 Address Instruction Operands (041) "BSET 00000 000000 #0000 D00100 D00101 "BSET(041) 00001 (100) #0000 D00000 D00200 D00100 D00101 (100) D00001 D00201 00002 BIN(100) D00000 (452) D00200 D00200 D00202 00003 BIN(100) D00001 (452) D00201 D00204 D00201 00004 FLT(425)
Page 308: Floating To 16-Bit: Fix(450)
Floating-point Math Instructions Section 5-21 Calculations Example ) 100 Distance r = Distance r = = 141.4214 Angle θ = tan Angle θ = tan –1 –1 = 45.0 DM Contents D00000 0 1 0 0 D00100 0 1 4 1 θ...
Page 309: Floating To 32-Bit: Fixl(451)
Floating-point Math Instructions Section 5-21 Only the integer portion of the floating-point data is converted, and the fraction portion is truncated. For example, “3.5” becomes “3,” and “–3.5” becomes “–3.” Precautions S must be floating-point data between –32,768 and 32,767. Note Refer to page 115 for general precautions on operand data areas.
Page 310: 16-Bit To Floating: Flt(452)
Floating-point Math Instructions Section 5-21 5-21-3 16-BIT TO FLOATING: FLT(452) (CVM1 V2) Ladder Symbol Operand Data Areas (452) S: Source word CIO, G, A, T, C, #, DM, DR, IR R: First result word CIO, G, A, DM Variations FLT(452) Description When the execution condition OFF, FLT(452) is not executed.
Page 311: Floating-Point Add: +F(454)
Floating-point Math Instructions Section 5-21 Flags ER (A50003): The content of a*DM word is not BCD when set for BCD. EQ (A50006): The exponent and mantissa of the result are 0. N (A50008): The result of the conversion is a negative number. 5-21-5 FLOATING-POINT ADD: +F(454) (CVM1 V2) Ladder Symbol...
Page 312: Floating-Point Subtract: -F(455)
Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-6 FLOATING-POINT SUBTRACT: –F(455) (CVM1 V2) Ladder Symbol Operand Data Areas (455) Mi: First minuend word CIO, G, A, T, C, #, DM –F Su: First subtrahend word...
Page 313: Floating-Point Multiply: *F(456)
Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-7 FLOATING-POINT MULTIPLY: *F(456) (CVM1 V2) Ladder Symbol Operand Data Areas (456) Md: First multiplicand word CIO, G, A, T, C, #, DM Mr: First multiplier word CIO, G, A, T, C, #, DM...
Page 314: Floating-Point Divide: /F(457)
Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-8 FLOATING-POINT DIVIDE: /F(457) (CVM1 V2) Ladder Symbol Operand Data Areas (457) Dd: First dividend word CIO, G, A, T, C, #, DM Dr: First divisor word CIO, G, A, T, C, #, DM...
Page 315: Degrees To Radians: Rad(458)
Floating-point Math Instructions Section 5-21 UF (A50010): Absolute value of the result is less than the minimum value that can be expressed for floating-point data. 5-21-9 DEGREES TO RADIANS: RAD(458) (CVM1 V2) Ladder Symbol Operand Data Areas (458) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM...
Page 316: Radians To Degrees: Deg(459)
Floating-point Math Instructions Section 5-21 5-21-10 RADIANS TO DEGREES: DEG(459) (CVM1 V2) Ladder Symbol Operand Data Areas (459) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations RAD(459) Description When the execution condition OFF, DEG(459) is not executed.
Page 317: Sine: Sin(460)
Floating-point Math Instructions Section 5-21 5-21-11 SINE: SIN(460) (CVM1 V2) Ladder Symbol Operand Data Areas (460) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations SIN(460) Description When the execution condition OFF, SIN(460) is not executed. When the execu- tion condition is ON, SIN(460) computes the sine of the angle (in radians) ex- pressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.
Page 318: Cosine: Cos(461)
Floating-point Math Instructions Section 5-21 5-21-12 COSINE: COS(461) (CVM1 V2) Ladder Symbol Operand Data Areas (461) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations COS(461) Description When the execution condition OFF, COS(461) is not executed. When the execu- tion condition is ON, COS(461) computes the cosine of the angle (in radians) expressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.
Page 319: Tangent: Tan(462)
Floating-point Math Instructions Section 5-21 5-21-13 TANGENT: TAN(462) (CVM1 V2) Ladder Symbol Operand Data Areas (462) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations TAN(462) Description When the execution condition OFF, TAN(462) is not executed. When the execu- tion condition is ON, TAN(462) computes the tangent of the angle (in radians) expressed as the 32-floating-point content of S and S+1, and places the result in R and R+1.
Page 320: Sine To Angle: Asin(463)
Floating-point Math Instructions Section 5-21 N (A50008): The result is a negative number. OF (A50009): The absolute value of the result is greater than the maximum value that can be expressed for floating-point data. UF (A50010): OFF when the computation is executed. 5-21-14 SINE TO ANGLE: ASIN(463) (CVM1 V2)
Page 321: Cosine To Angle: Acos(464)
Floating-point Math Instructions Section 5-21 OF (A50009): OFF when the computation is executed. UF (A50010): OFF when the computation is executed. 5-21-15 COSINE TO ANGLE: ACOS(464) (CVM1 V2) Ladder Symbol Operand Data Areas (464) S: First source word CIO, G, A, T, C, #, DM ACOS R: First result word CIO, G, A, DM...
Page 322: Tangent To Angle: Atan(465)
Floating-point Math Instructions Section 5-21 5-21-16 TANGENT TO ANGLE: ATAN(465) (CVM1 V2) Ladder Symbol Operand Data Areas (465) S: First source word CIO, G, A, T, C, #, DM ATAN R: First result word CIO, G, A, DM Variations ATAN(465) Description When the execution condition OFF, ATAN(465) is not executed.
Page 323: Square Root: Sqrt(466)
Floating-point Math Instructions Section 5-21 5-21-17 SQUARE ROOT: SQRT(466) (CVM1 V2) Ladder Symbol Operand Data Areas (466) S: First source word CIO, G, A, T, C, #, DM SQRT R: First result word CIO, G, A, DM Variations SQRT(466) Description When the execution condition OFF, SQRT(466) is not executed.
Page 324: Exponent: Exp(467)
Floating-point Math Instructions Section 5-21 5-21-18 EXPONENT: EXP(467) (CVM1 V2) Ladder Symbol Operand Data Areas (467) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations EXP(467) Description When the execution condition OFF, EXP(467) is not executed. When the execu- tion condition is ON, EXP(467) computes the exponent for the 32-floating-point content of S and S+1, and places the result in R and R+1.
Page 325: Logarithm: Log(468)
Floating-point Math Instructions Section 5-21 5-21-19 LOGARITHM: LOG(468) (CVM1 V2) Ladder Symbol Operand Data Areas (468) S: First source word CIO, G, A, T, C, #, DM R: First result word CIO, G, A, DM Variations LOG(468) Description When the execution condition OFF, LOG(468) is not executed. When the execu- tion condition is ON, LOG(468) computes the natural logarithm for the 32-float- ing-point content of S and S+1, and places the result in R and R+1.
Page 326: Increment/Decrement Instructions
Increment/Decrement Instructions Section 5-22 5-22 Increment/Decrement Instructions The Increment/Decrement Instructions all either increment or decrement a num- ber by one. The content of the source word is overwritten with the instruction result for all increment/decrement instructions. 5-22-1 INCREMENT BCD: INC(090) Ladder Symbol Operand Data Area (090)
Page 327: Increment Binary: Incb(092)
Increment/Decrement Instructions Section 5-22 Example When CIO 000000 is ON in the following example, the content of D00010 is decremented by 1 as a BCD value. 0000 Address Instruction Operands (091) DEC D00010 00000 000000 00001 DEC(091) D00010 D00010 D00010 –...
Page 328: Decrement Binary: Decb(093)
Increment/Decrement Instructions Section 5-22 5-22-4 DECREMENT BINARY: DECB(093) Ladder Symbol Operand Data Area (093) Wd: Word CIO, G, A, DM, DR, IR DECB Wd Variations j DECB(093) Description When the execution condition is OFF, DECB(093) is not executed. When the ex- ecution condition is ON, DECB(093) decrements Wd, without affecting carry (CY).
Page 329: Double Decrement Bcd: Decl(095)
Increment/Decrement Instructions Section 5-22 Example When CIO 000000 is ON in the following example, the content of D0100 and D01001 is incremented by 1 as a BCD value. 0000 Address Instruction Operands (094) INCL D01000 00000 000000 00001 INCL(094) D01000 Wd+1: D01001 Wd: D01000 Wd+1: D01001...
Page 330: Double Decrement Binary: Dcbl(097)
Increment/Decrement Instructions Section 5-22 Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of Wd+1 after execution. Example When CIO 000000 is ON in the following example, the content of CIO 0500 and CIO 0501 is incremented by 1 as a binary value.
Page 331: Special Math Instructions
Special Math Instructions Section 5-23 5-23 Special Math Instructions The Special Math Instructions preform special arithmetic operations. MAX(165) searches a range of words for the maximum value. MIN(166) searches a range of words for the minimum value. SUM(167) adds a range of words. ROOT(140) finds the square root of a value.
Page 332: Find Minimum: Min(166)
Special Math Instructions Section 5-23 Example When CIO 000000 is ON in the following example, MAX(165) outputs to D00500 the maximum value within the 10-word range from CIO 0200 to CIO 0209. Be- cause bit 14 of C is ON, the lower address of the two addresses within the range that contain the maximum value is output to IR0.
Page 333 Special Math Instructions Section 5-23 When bit 15 of C is OFF, data within the range is treated as unsigned binary and when it is ON the data is treated as signed binary. Refer to 3-2 Data Area Struc- ture for information on signed and unsigned binary data. 15 14 13 12 11 Number of words in range (N)
Page 334: Sum: Sum(167)
Special Math Instructions Section 5-23 5-23-3 SUM: SUM(167) Ladder Symbol Operand Data Areas (167) C: Control word CIO, G, A, #, DM, DR, IR word in range CIO, G, A, T, C, DM Variations D: 1 destination word CIO, G, A, DM j SUM(167) Description When the execution condition is OFF, SUM(167) is not executed.
Page 335: Bcd Square Root: Root(140)
Special Math Instructions Section 5-23 C : # 1 0 0 Binary Unsigned D00000 3F2A $2000 D00001 51C3 $2001 D00002 E02A $2002 D00003 7C9F $2003 D00004 2A20 $2004 10 words D00005 A827 $2005 D00006 2A20 $2006 D00007 E02A $2007 D00008 C755 $2008 D00009...
Page 336 Special Math Instructions Section 5-23 Example The following example shows how to take the square root of a 4-digit number and then round the result. When CIO 000000 is ON, first the words to be used are cleared to all zeros and then the value whose square root is to be taken is moved to Sq+1.
Page 337: Binary Root: Rotb(274)
Special Math Instructions Section 5-23 5-23-5 BINARY ROOT: ROTB(274) (CVM1 V2) Ladder Symbol Operand Data Areas (274) S: First source word CIO, G, A, T, C, #, DM ROTB R: Result word CIO, G, A, DM, DR, IR Variations ROTB(274) Description When the execution condition is OFF, ROTB(274) is not executed.
Page 338: Floating Point Divide: Fdiv(141)
Special Math Instructions Section 5-23 5-23-6 FLOATING POINT DIVIDE: FDIV(141) Ladder Symbol Operand Data Areas (141) Dd: 1 dividend word CIO, G, A, T, C, DM FDIV Dr: 1 divisor word CIO, G, A, T, C, DM Variations R: 1 result word CIO, G, A, DM j FDIV(141)
Page 339 Special Math Instructions Section 5-23 First the original numbers must be placed in floating-point form. Because the numbers are originally without decimal points, the exponent will be 4 (e.g., 3452 would equal 0.3452 x 10 ). All of the moves are to place the proper data into con- secutive words for the final division, including the exponent and zeros.
Page 340: Arithmetic Process: Apr(142)
Special Math Instructions Section 5-23 5-23-7 ARITHMETIC PROCESS: APR(142) Ladder Symbol Operand Data Areas (142) C: Control word CIO, G, A, #, DM, DR, IR S: Source data CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR j APR(142) Description...
Page 341 Special Math Instructions Section 5-23 Source data Result S: D00010 R: D00200 –1 –1 –2 –3 –4 Result data has four significant Enter input data not exceeding #0900 digits, fifth in BCD form. and higher digits are ignored. The result for cos(0) will be 0.9999, not 1.
Page 342: Pid And Related Instructions
PID and Related Instructions Section 5-24 Content Coordinate 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 D00000 $C00B D00001 $0000 (m–1 = 11: 12 line D00002 $0000 segments) D00003 $0005 D00004 $0F00 Output and D00005 $001A...
Page 343 PID and Related Instructions Section 5-24 If the manipulated variable after the PID action exceeds the upper limit, the Greater Than (>) Flag (A50005) will turn ON and the result will be output at the upper limit. If the manipulated variable after the PID action is less than the lower limit, the Less Than (<) Flag (A50007) will turn ON and the result will be output at the lower limit.
Page 344 PID and Related Instructions Section 5-24 Item Contents Setting range 0: 8 bits 5: 13 bits Input range The number of input data bits. 1: 9 bits 1: 9 bits 6: 14 bits 6: 14 bits Output range The number of output data bits. {The number 2: 10 bits 7: 15 bits of output bits is automatically the same as the...
Page 345 PID and Related Instructions Section 5-24 PID Control Method PID control actions are executed by means of PID control with feed-forward con- trol (two degrees of freedom). When overshooting is prevented with simple PID control, stabilization of distur- bances is slowed (1). If stabilization of disturbances is speeded up, on the other hand, overshooting occurs and response toward the target value is slowed (2).
Page 346 PID and Related Instructions Section 5-24 Integral Action (I) Combining integral action with proportional action reduces the offset according to the time that has passed. The strength of the integral action is indicated by the integral time, which is the time required for the manipulated variable of the inte- gral action to reach the same level as the manipulated variable of the proportion- al action with respect to the step deviation, as shown in the following illustration.
Page 347 PID and Related Instructions Section 5-24 The strength of the derivative action is indicated by the derivative time, which is the time required for the manipulated variable of the derivative action to reach the same level as the manipulated variable of the proportional action with re- spect to the step deviation, as shown in the following illustration.
Page 348 PID and Related Instructions Section 5-24 Forward action: MV is increased when the PV is larger than the SV. Reverse action: MV is increased when the PV is smaller than the SV. Reverse Action Forward Action Proportional Proportional band band 100% 100% Manipulated...
Page 349: Limit Control: Lmt(271)
PID and Related Instructions Section 5-24 Precautions PID data must be within prescribed ranges. Note Refer to page 115 for general precautions on operand data areas. Flags ER (A50003): PID data is outside of the allowable range. The actual sampling period is two or more times the sam- pling period that has been set.
Page 350: Dead-Band Control: Band(272)
PID and Related Instructions Section 5-24 Example When CIO 000000 turns ON in the following example, one of the following will occur: If the binary content of CIO 0001 is within the range specified by the content of D00100 and D00101, the content of CIO 0001 will be output to D00110. If the binary content of CIO 0001 is greater than the content of D00101, the content of D00101 will be output to D00110.
Page 351 PID and Related Instructions Section 5-24 If the input data (S) is greater than or equal to the lower limit (C) and less than or equal to the upper limit (C+1), 0000 will be output to D and the Equals Flag (A50006) will turn ON.
Page 352: Dead-Zone Control: Zone(273)
PID and Related Instructions Section 5-24 5-24-4 DEAD-ZONE CONTROL: ZONE(273) (CVM1 V2) Ladder Symbol Operand Data Areas (273) S: Input word CIO, G, A, T, C, #, DM, DR, IR ZONE C: First bias word CIO, G, A, T, C, DM Variations D: Output word CIO, G, A, T, C, DM, DR, IR...
Page 353: Logic Instructions
Logic Instructions Section 5-25 Example When CIO 000000 turns ON in the following example, one of the following will occur: If the binary content of CIO 0001 is less than zero, the result of CIO 0001 plus D00100 will be output to D00110. If the binary content of CIO 0001 is equal to zero, 0000 will be output to D00110.
Page 354: Logical Or: Orw(131)
Logic Instructions Section 5-25 CIO 0010 CIO 0020 D00200 5-25-2 LOGICAL OR: ORW(131) Ladder Symbol Operand Data Areas (131) : Input 1 CIO, G, A, T, C, #, DM, DR, IR : Input 2 CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR...
Page 355: Exclusive Or: Xorw(132)
Logic Instructions Section 5-25 5-25-3 EXCLUSIVE OR: XORW(132) Ladder Symbol Operand Data Areas (132) : Input 1 CIO, G, A, T, C, #, DM, DR, IR XORW : Input 2 CIO, G, A, T, C, #, DM, DR, IR Variations R: Result word CIO, G, A, DM, DR, IR j XORW(132)
Page 356: Double Logical And: Andl(134)
Logic Instructions Section 5-25 Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R after execution. Example When CIO 000000 is ON in the following example, the logical exclusive NOR is taken of corresponding bits in CIO 0010 and CIO 0020 and the results is placed in corresponding bits of D00200.
Page 357: Double Logical Or: Orwl(135)
Logic Instructions Section 5-25 CIO 0011 CIO 0010 CIO 0021 CIO 0020 D00201 D00200 5-25-6 DOUBLE LOGICAL OR: ORWL(135) Ladder Symbol Operand Data Areas (135) : Input 1 CIO, G, A, T, C, #, DM ORWL : Input 2 CIO, G, A, T, C, #, DM Variations R: Result word CIO, G, A, DM...
Page 358: Double Exclusive Or: Xorl(136)
Logic Instructions Section 5-25 5-25-7 DOUBLE EXCLUSIVE OR: XORL(136) Ladder Symbol Operand Data Areas (136) : Input 1 CIO, G, A, T, C, #, DM XORL : Input 2 CIO, G, A, T, C, #, DM Variations R: Result word CIO, G, A, DM j XORL(136) Description...
Page 359: Complement: Com(138)
Logic Instructions Section 5-25 Content of *DM word is not BCD when set for BCD. Flags ER (A50003): EQ (A50006): The result is 0. N (A50008): Shows the status of bit 15 of R+1 after execution. Example When CIO 000000 is ON in the following example, the logical exclusive NOR is taken of corresponding bits in CIO 0010 to CIO 0011 and CIO 0020 to CIO 0020 and the results is placed in corresponding bits of D00200 and D00201.
Page 360: Double Complement: Coml(139)
Logic Instructions Section 5-25 D02000 Original Complement 5-25-10 DOUBLE COMPLEMENT: COML(139) Ladder Symbol Operand Data Area (139) Wd: Word CIO, G, A, DM COML Wd Variations j COML(139) Description When the execution condition is OFF, COML(139) is not executed. When the execution condition is ON, COML(139) turns OFF all ON bits and turns ON all OFF bits in Wd and Wd+1.
Page 361: Time Instructions
Time Instructions Section 5-26 5-26 Time Instructions The first two Time Instructions convert time formats. The last two Time Instruc- tions add/subtract time from calendar values. 5-26-1 HOURS TO SECONDS: SEC(143) Ladder Symbol Operand Data Areas (143) S: 1 source word CIO, G, A, T, C, #, DM R: 1 result word CIO, G, A, DM...
Page 362: Seconds To Hours: Hms(144)
Time Instructions Section 5-26 5-26-2 SECONDS TO HOURS: HMS(144) Ladder Symbol Operand Data Areas (144) S: 1 source word CIO, G, A, T, C, #, DM R: 1 result word CIO, G, A, DM Variations j HMS(144) Description When the execution condition is OFF, HMS(144) is not executed. When the ex- ecution condition is ON, HMS(144) converts time notation in seconds to an equivalent time in hours/minutes/seconds.
Page 363 Time Instructions Section 5-26 The following table shows the format of calendar information. The format is the same for the results output to R, R+1, and R+2. Word Bits Contents Possible values 00 to 07 Seconds 00 to 59 08 to 15 Minutes 00 to 59 00 to 07 Hours 00 to 23 (24-hour system)
Page 364: Calendar Subtract: Csub(146)
Time Instructions Section 5-26 5-26-4 CALENDAR SUBTRACT: CSUB(146) Ladder Symbol Operand Data Areas (146) C: 1 calendar word CIO, G, A, T, C, DM CSUB T: 1 time word CIO, G, A, T, C, #, DM Variations R: 1 result word CIO, G, A, DM j CSUB(146) Description...
Page 365: Clock Compensation: Date(179)
Time Instructions Section 5-26 C + 2 : D00102 C + 1 : D00101 C : D00100 T + 1 : D02001 1532 T : D02000 R + 2 : D00502 R + 1 : D00501 R : D00500 5-26-5 CLOCK COMPENSATION: DATE(179) (CVM1 V2) Ladder Symbol Operand Data Areas...
Page 366: Special Instructions
Special Instructions Section 5-27 Example When CIO 000000 is ON in the following example, the internal clock setting will be changed according to the content of D00100 through D00103. 000000 (179) Address Instruction Operands DATE D00100 00000 000000 00001 DATE(179) D00100 D00100 D00101...
Page 367 Special Instructions Section 5-27 When executed with an ON execution condition, both FAL(006) and FALS(007) cause an error code to be output to A400. The error code identifies the FAL num- ber (FAL(006) and FALS(007) use the same FAL numbers) and whether the er- ror is an FAL or FALS error, as shown in the table.
Page 368: Failure Point Detection: Fpd(177)
Special Instructions Section 5-27 Flags ER (A50003): N contains improper data. Content of *DM word is not BCD when set for BCD. A40215: The FAL Instruction Flag will be turned ON when an FAL(006) instruction is executed. A40106: The FALS Instruction Flag will be turned ON when an FALS(007) instruction is executed.
Page 369 Special Instructions Section 5-27 The following diagram illustrates the type of program section that can be diag- nosed with FPD(177). The instruction block that is diagnosed by FPD(177) starts at the fist LD after FPD(177) (excluding LD for TR bits) and ends at the next output or special (right-hand) instruction (except for OUT for TR bits).
Page 370 Special Instructions Section 5-27 When IR 00000 to IR 00003 are ON in the following example, the normally closed condition IR 00002 would be found as the cause of the diagnostic output not turning ON. 00000 00002 Diagnostic output 00001 00003 The logic diagnosis operation runs independently from the time monitoring op- eration.
Page 371 Special Instructions Section 5-27 Words D+1 to D+8 contain information in ASCII displayed on a Peripheral Device along with the bit address when FPD(177) is executed. Words D+5 to D+8 contain the message preset by the user as shown in the following table.
Page 372 Special Instructions Section 5-27 In the following example, it is assumed that CIO 000001 through CIO 000004 are all ON, thus CIO 000003 is output as the address of the bit responsible for CIO 002000 not turning ON. A500 Address Instruction Operands First Scan Flag (030)
Page 373: Maximum Cycle Time Extend: Wdt(178)
Special Instructions Section 5-27 5-27-3 MAXIMUM CYCLE TIME EXTEND: WDT(178) (CVM1 V2) Ladder Symbol Operand Data Area (178) T: Timer value # (0000 to 3999) Variations j WDT(178) Generally, the maximum cycle time is designated in the PC Setup, and if the cycle time exceeds the designated value, a fatal error (Cycle Time Too Long) will occur.
Page 374: I/O Refresh: Iorf(184)
Special Instructions Section 5-27 5-27-4 I/O REFRESH: IORF(184) Ladder Symbol Operand Data Areas (184) St: Starting word IORF E: Ending word Variations j IORF(184) Description When the execution condition is OFF, IORF(184) is not executed. When the ex- ecution condition is ON, all words between St and E will be refreshed. This will be in addition to the normal I/O refresh performed during the CPU’s scan.
Page 375 Special Instructions Section 5-27 Bits 00 to 06 specify the Unit to which the characters will be output (specifics are shown in the following diagram). Bit 07 determines whether the source data is hexadecimal (OFF) or 7-segment display code (ON). Bit 08 determines whether the characters will flash (ON) or not (OFF).
Page 376: Select Em Bank: Embc(171)
Special Instructions Section 5-27 D15000 Rack no. 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 Rack no. 2 Set to 0 Set to 0 I/O Interface Unit Rack no. 1 RT address 0 Segment specified Blinking indication Automatic indication...
Page 377: Data Search: Srch(164)
Special Instructions Section 5-27 Example When CIO 000000 is ON in the following example, the current EM bank is changed to bank 3. The contents of A511 would change to “8003” to indicate that bank 3 is the current bank. 0000 Address Instruction...
Page 378: Flag/Register Instructions
Flag/Register Instructions Section 5-28 Wd 0500 89AB Memory address D00000 1234 $2000 D00001 5678 $2001 D00002 ABCD $2002 D00003 EF13 $2003 D00004 89AB $2004 Same data 10 words D00005 8860 $2005 D00006 90CD $2006 D00007 00FF $2007 D00008 89AB $2008 Same data D00009 810C $2009...
Page 379: Save Flags: Ccs(173)
Flag/Register Instructions Section 5-28 5-28-2 SAVE FLAGS: CCS(173) Ladder Symbol Variations j CCS(173) (173) Description When the execution condition is OFF, CCS(173) is not executed. When the ex- ecution condition is ON, CCS(173) records the current status of the Arithmetic Flags in the CPU for later retrieval by the CCL(172) instruction.
Page 380: Save Register: Regs(176)
STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 5-28-4 SAVE REGISTER: REGS(176) Ladder Symbol Operand Data Area (176) D: 1 destination word CIO, G, A, DM REGS Variations j REGS(176) Description When the execution condition is OFF, REGS(176) is not executed. When the ex- ecution condition is ON, REGS(176) copies the data from data registers DR0, DR1, and DR2 to D, D+1, and D+2, and copies the data from index registers IR0, IR1, and IR2 to D+3, D+4, and D+5.
Page 381 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 STEP DEFINE: STEP(008) Ladder Symbol Operand Data Area (008) B: Bit CIO, G, A STEP (008) STEP STEP START: SNXT(009) Ladder Symbol Operand Data Area (009) B: Bit CIO, G, A SNXT Description STEP(008) uses a control bit to define the beginning of a section of the program called a step.
Page 382 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 Two simple steps are shown below. In this example, the 1st step would be ex- ecuted from the time that CIO 00000 goes ON until CIO 000001 goes ON. The 2nd step would be executed for the time the CIO 000001 goes ON until CIO 000002 goes ON.
Page 383 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 Flags A50012: The Step Flag is turned ON for one cycle when STEP(008) is executed and if necessary it can be used to reset counters in steps as shown below. 0000 Address Instruction Operands (009) SNXT 001000...
Page 384 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 The following diagram demonstrates the flow of processing and the switches that are used for execution control. Process A Loading Process B Part Installation Process C Inspection/discharge The program for this process, shown below, utilizes the most basic type of step programming: each step is completed by a unique SNXT(009) that starts the next step.
Page 385: Step Define And Step Start: Step(008)/Snxt(009)
STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 Example 2: The following process requires that a product is processed in one of two ways, Branching Execution depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used.
Page 386 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 The program for this process, shown below, starts with two SNXT(009) instruc- tions that start processes A and B. Because of the way CIO 000001 (SW A1) and CIO 000002 (SW B1) are programmed, only one of these will be executed with an ON execution condition to start either process A or process B.
Page 387 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 The following diagram demonstrates the flow of processing and the switches that are used for execution control. Here, process A and process C are started together. When process A finishes, process B starts; when process C finishes, process D starts.
Page 388 STEP DEFINE and STEP START: STEP(008)/SNXT(009) Section 5-29 When both process B and process D have finished (i.e., when SW5 and SW6 turn ON), processes B and D are reset together by the SNXT(009) at the end of the programming for process B. Although there is no SNXT(009) at the end of process D, the control bit for it is turned OFF by executing SNXT(009) 050004.
Page 389: Subroutines
Subroutines Section 5-30 5-30 Subroutines Subroutines break large control tasks into smaller ones and enable you to reuse a given set of instructions. When the main program calls a subroutine, control is transferred to the subroutine and the subroutine instructions are executed. The instructions within a subroutine are written in the same way as main program code.
Page 390: Subroutine Call: Sbs(151)
Subroutines Section 5-30 Example When CIO 000000 is ON in the following example, the instructions between SBN(150) 001 and RET(152) are executed once before returning to execute the next instruction line after SBS(151). 0000 Address Instruction Operands (151) 00000 000000 00001 SBS(151) (Other instructions)
Page 391 Subroutines Section 5-30 the subroutine defined with SBN(150) 00). The following diagram illustrates two levels of nesting. SBN(150) 010 SBN(150) 011 SBN(150) 012 SBS(151) 010 SBS(151) 011 SBS(151) 012 RET(152) RET(152) RET(152) Although subroutines 00 through 31 can be called by using SBS(151), they are also activated by interrupt signals from Interrupt Input Units.
Page 392: Macro: Mcro(156)
Subroutines Section 5-30 5-30-3 MACRO: MCRO(156) (CVM1 V2) Ladder Symbol Operand Data Areas (156) N: Subroutine number 000 to 999 or 000 to 099 MCRO N S: First input parameter word CIO, G, A, T, C, DM Variations D: First output parameter word CIO, G, A, T, C, DM MCRO(156) Description...
Page 393 Subroutines Section 5-30 Main Program Subroutine Call CIO 0200 A200 CIO 0201 A201 CIO 0202 A202 CIO 0203 A203 Input (Processing) Output CIO 0300 A204 CIO 0301 A205 CIO 0302 A206 CIO 0303 A207 Return Program Examples The following examples show how MCRO(156) can be used to simplify a pro- gram.
Page 394: Interrupt Control
Interrupt Control Section 5-31 Address Instruction Operands A50013 (156) MCRO 010 0000 0100 00000 A50013 00001 MCRO(156) (156) 0000 MCRO 010 0002 0105 0100 (156) 00002 MCRO(156) MCRO 010 0005 0120 0002 0105 (156) MCRO 010 0010 0150 00003 MCRO(156) 0005 0120 00004...
Page 395 Interrupt Control Section 5-31 For each Interrupt Input Unit, bits 00 through 07 may be used for interrupt sig- nals. Bits 08 through 15 are not used. When one of the bits assigned to an Inter- rupt Input Unit turns ON, the interrupt program associated with it is called and executed.
Page 396 Interrupt Control Section 5-31 When the I/O interrupt setting in the PC Setup (execution controls 2) is set to hold other I/O interrupts, an incoming I/O interrupt must wait until the first I/O in- terrupt is finished, regardless of the priority ranking of the two I/O interrupts. The following example shows program execution with this I/O interrupt setting.
Page 397: Interrupt Mask: Msks(153)
Interrupt Control Section 5-31 5-31-1 INTERRUPT MASK: MSKS(153) Ladder Symbol Operand Data Areas (153) N: Interrupt source # (0 to 5) MSKS S: Data source word CIO, G, A, T, C, #, DM, DR, IR Variations j MSKS(153) Description When the execution condition is OFF, MSKS(153) is not executed. When the ex- ecution condition is ON, MSKS(153) masks interrupts from Interrupt Input Units (so that they are recorded but ignored) if N is 0 to 3 or sets the time interval for scheduled interrupts if N is 4 or 5.
Page 398: Clear Interrupt: Cli(154)
Interrupt Control Section 5-31 Example In the following example, inputs 0 to 3 of Interrupt Input Unit 0 are unmasked, and inputs 4 to 7 are masked when CIO 000000 is ON. 0000 Address Instruction Operands (153) MSKS 0 D00100 00000 000000 00001...
Page 399 Interrupt Control Section 5-31 Interrupt program 3 Interrupt program 0 Interrupt program 1 Interrupt program 2 Interrupt program 3 Numbers 4 or 5 designate a scheduled interrupt, and CLI(154) sets the time to the first interrupt. The time to the first interrupt can be set between 10 and 99,990 ms, depending on both the content of S and the time unit set in the PC Setup.
Page 400: Read Mask: Mskr(155)
Interrupt Control Section 5-31 The control flow logic of the main program is unaffected by execution of the inter- rupt program, i.e., immediately after the interrupt program has finished execu- tion, control returns to the point in the main program where it was suspended. Main Program Area Address Instruction Operands...
Page 401: Stack Instructions
Stack Instructions Section 5-32 Example In the following example, MSKR(155) writes the current mask status of Interrupt Input Unit number 2 into D00100 when CIO 000000 is ON. jMSKR(155) writes the time interval for scheduled interrupt 0 into CIO 1500 the next execution after CIO 000001 turns ON.
Page 402: Push Onto Stack: Push(161)
Stack Instructions Section 5-32 Note Refer to page 115 for general precautions on operand data areas. Flags ER (A50003): Content of N is less than 0003, or is not BCD. Content of *DM word is not BCD when set for BCD. Example When CIO 000000 is ON in the following example, SSET(160) defines a 7-word stack from D00000 to D00006.
Page 403: Last In First Out: Lifo(162)
Stack Instructions Section 5-32 Example When CIO 000000 is ON in the following example, PUSH(161) is used to write the data in CIO 1000 to the 7-word stack from D00000 to D00006. The stack pointer contains the memory address of D00002, so the data in CIO 1000 is co- pied to D00002.
Page 404: First In First Out: Fifo(163)
Stack Instructions Section 5-32 Memory Memory address address D00000 $2006 (Final stack address) $2000 D00000 $2006 (Final stack address) $2000 D00001 $2004 (Stack pointer) $2001 D00001 $2003 (Stack pointer) $2001 D00002 ABCD $2002 D00002 ABCD $2002 D00003 37B4 $2003 D00003 37B4 (Moved to CIO 0200) $2003 D00004 0000 $2004...
Page 405: Data Tracing
Data Tracing Section 5-33 5-33 Data Tracing Data tracing can be used to facilitate debugging programs and is described in detail in the CVSS Operation Manual: Online . This section shows the ladder symbols for TRSM(170) and MARK(171) and provides example programs. 5-33-1 TRACE MEMORY SAMPLING: TRSM(170) Ladder Symbol (170)
Page 406 Data Tracing Section 5-33 made will be recorded as the trace memory (negative delay), or that more sam- ples will be made before they are recorded (positive delay). The sampled data is written to trace memory, jumping to the beginning of the memory area once the end has been reached and continuing up to the start marker.
Page 407: Mark Trace: Mark(174)
Data Tracing Section 5-33 5-33-2 MARK TRACE: MARK(174) Ladder Symbol Operand Data Area (174) N: Mark number MARK Description Like TRSM(170), MARK(174) is used in the program to mark locations where specified data is to be stored in Trace Memory. Two words may be designated for tracing, and each time the MARK(174) instruction is executed, the word ad- dress, content, and mark number are stored in Trace Memory.
Page 408: Memory Card Instructions
Memory Card Instructions Section 5-34 5-34 Memory Card Instructions Memory Card Instructions all involve the transfer of data to and from the Memory Card in the memory card drive. The instructions described in this section can thus only be used if there is a Memory Card in the drive. Exercise care when transferring a very large number of words, because it can greatly increase the overall cycle time.
Page 409 Memory Card Instructions Section 5-34 When FILR(180) is executed, the CPU first checks whether the ER Flag (A50003) is ON, then processes the data transfer and following instructions in parallel, so check the Memory Card Instruction Flag (A34313) to verify that FILR(180) has been completed correctly.
Page 410: Write Data File: Filw(181)
Memory Card Instructions Section 5-34 5-34-2 WRITE DATA FILE: FILW(181) Ladder Symbol Operand Data Areas (181) N: Words to transfer CIO, G, A, T, C, #, DM, DR, IR FILW S: 1 source word CIO, G, A, T, C, DM Variations C: 1 control word...
Page 411 Memory Card Instructions Section 5-34 Example In the following example the data in D01000 to D01019 is written over the 20 words in memory card data file “ABCD” beginning at the 17 word of file. Here, the content of CIO 0300 would be 0020 (BCD) to indicate reading 20 words.
Page 412: Read Program File: Filp(182)
Memory Card Instructions Section 5-34 5-34-3 READ PROGRAM FILE: FILP(182) Ladder Symbol Operand Data Area (182) C: 1 control word CIO, G, A, T, C, DM FILP Variations j FILP(182) Description When the execution condition is OFF, FILP(182) is not executed. When the ex- ecution condition is ON, FILP(182) reads the ladder program file ( filename .LDP) specified in C+1 to C+4 from the Memory Card, and writes the data over the cur- rent ladder program beginning at the instruction just after FILP(182).
Page 413 Memory Card Instructions Section 5-34 If the program file is shorter than the original ladder program from FILP(182) to END(001) and doesn’t end in END(001), be sure that the program file doesn’t overwrite only the first part of an instruction in the original ladder program creat- ing an instruction format error.
Page 414: Change Step Program: Flsp(183)
Memory Card Instructions Section 5-34 CIO 0500 0 0 0 0 Overwrite CIO 0501 4 1 4 2 “A,” “B” CIO 0502 4 3 4 4 “C,” “D” CIO 0503 2 0 2 0 CIO 0504 2 0 2 0 5-34-4 CHANGE STEP PROGRAM: FLSP(183) Ladder Symbol Operand Data Areas...
Page 415 Memory Card Instructions Section 5-34 The contents of a subchart will be changed if the step number of a subchart dummy step is specified for N. The number of the steps in the subchart can be changed, as shown in the following diagram. ST0500 0500 ST0100...
Page 416: Special I/O Instructions
Special I/O Instructions Section 5-35 Example When CIO 000000 is ON in the following example with the memory contents shown, the contents of step 0050 will be overwritten with the contents of ABCD.SFC. The structure of the SFC program will not change, but the contents of the action block for step 0050 will be replaced with the contents of ABCD.SFC.
Page 417 Special I/O Instructions Section 5-35 This instruction cannot be used to read data from Special I/O Units mounted to Slave Racks in SYSMAC BUS Remote I/O Systems. It can be used for certain Special I/O Units mounted to newer version of SYSMAC BUS/2 Remote I/O Sys- tems.
Page 418: I/O Read 2: Rd2(280)
Special I/O Instructions Section 5-35 Example When CIO 000000 is ON in the following example, the number of words speci- fied in CIO 0001 is read through CIO 0003 (the I/O word allocated to the Special I/O Unit) and stored at consecutive words starting at D00010. The following program section uses a self-holding bit to ensure that the read op- eration is executed even if the Special I/O Unit (or Slave Rack) is busy when READ(190) is executed.
Page 419 Special I/O Instructions Section 5-35 RD2(280) carries out data exchange with the Special I/O Unit via the I/O area, so the time required to complete execution depends on the I/O refresh interval (i.e., the cycle time). Be sure that there is a Special I/O Unit mounted. If no Special I/O Unit is mounted, RD2(280) execution will continue without stopping.
Page 420: I/O Write: Writ(191)
Special I/O Instructions Section 5-35 PC Memory Special I/O Unit Memory Beginning address S: Source word to be read Words allocated to Special I/O Unit (CIO Area) Number of words to be read D: First destination word 5-35-3 I/O WRITE: WRIT(191) Ladder Symbol Operand Data Areas (191)
Page 421 Special I/O Instructions Section 5-35 and the Carry Flag (A50004) will turn ON. Be sure to control execution of these instructions so that no more than two are being executed simultaneously for Units connected under the same Master. This instruction cannot be used to write data to Special I/O Units mounted to Slave Racks in SYSMAC BUS Remote I/O Systems.
Page 422 Special I/O Instructions Section 5-35 The following program section uses a self-holding bit to ensure that the write op- eration is executed even if the Special I/O Unit (or Slave Rack) is busy when WRIT(191) is executed. The type of programming is also effective when the read operation requires more than one cycle.
Page 423: I/O Write 2: Wr2(281)
Special I/O Instructions Section 5-35 5-35-4 I/O WRITE 2: WR2(281) (CVM1 V2) Ladder Symbol Operand Data Areas (281) C: Control word CIO, G, A, T, C, #, DM, DR, IR S: First source word CIO, G, A, T, C, DM D: Destination word Description When the execution condition is OFF, WR2(281) is not executed.
Page 424 Special I/O Instructions Section 5-35 Example When CIO 000001 is ON in the following example, the 16 words beginning with D00300 are transferred in order through CIO 0002 and are written in order to words 00 through 0F in the Special I/O Unit‘s memory area. 0000 Address Instruction Operands...
Page 425: Network Instructions
Network Instructions Section 5-36 5-36 Network Instructions The Network Instructions are used for communicating with or control PCs or oth- er Units linked through the SYSMAC NET Link System or SYSMAC LINK Sys- tem. The first two Network Instructions are used to control the access right to the PC from both local and remote Peripheral Devices.
Page 426: Enable Access: Iors(188)
Network Instructions Section 5-36 5-36-2 ENABLE ACCESS: IORS(188) Ladder Symbol (188) IORS Description When the execution condition is OFF, IORS(188) is not executed. When the ex- ecution condition is ON, both read and write access to PC memory from Periph- eral Devices is enabled.
Page 427: Network Send: Send(192)
Network Instructions Section 5-36 Example The following example shows the display that would be produced for the instruc- tion and data given when CIO 000000 is ON. If CIO 000001 goes ON, message 0 will be cleared. The display message number must be set to 0 in the Peripheral Device before executing the instruction.
Page 428 Network Instructions Section 5-36 Control Data SYSMAC NET Link Systems Set the destination node number to $FF to send the data to all nodes in the des- ignated network or to $00 to send to a destination within the node of the PC ex- ecuting the send.
Page 429 Network Instructions Section 5-36 Note 1. Set the destination network address to $00 when transmitting within the lo- cal network. In this case, the network of the Link Unit with the lowest unit number will be selected if the PC belongs to more than one network. 2.
Page 430: Network Receive: Recv(193)
Network Instructions Section 5-36 5-36-5 NETWORK RECEIVE: RECV(193) Ladder Symbol Operand Data Areas (193) S: 1 source word CIO, G, A, T, C, DM RECV D: 1 destination word CIO, G, A, T, C, DM Variations C: 1 control word CIO, G, A, T, C, DM j RECV(193) Description...
Page 431 Network Instructions Section 5-36 3. Indicates a Unit as shown in the following table. Unit Setting SYSMAC NET Link or SYSMAC LINK $10 to $1F: Unit numbers 0 to F Unit $FE: The local Unit SYSMAC BUS/2 Master, BASIC Unit, $10 to $1F: Unit numbers 0 to F or Personal Computer Unit SYSMAC BUS/2 Group 2 Slave...
Page 432: Deliver Command: Cmnd(194)
Network Instructions Section 5-36 Example The following example is for receiving from a PC through a SYSMAC NET Link System. When CIO 000000 is ON, the RECV(193) transfers the content of CIO 0101 through CIO 0105 of the PC on node 3 of network 1, to D05001 through D05005 of the PC executing RECV(193).
Page 433 Network Instructions Section 5-36 Control Data The control words, beginning with C, specify the number of bytes of control data to be sent, the number of bytes of response data to be received, the destination node, and other parameters. Some control data parameters depend on whether a transmission is being received in a SYSMAC NET Link System or a SYSMAC LINK System.
Page 434 Network Instructions Section 5-36 Do not change the control data during a transmission (i.e., while the correspond- ing Port Enabled Flag in A502 is OFF). The Execute Error Flag for the designated port will be turned ON if no response is received in the response monitoring time (C+5), the amount of command data transmitted exceeds the maximum for the system, or the response data exceeds the number of bytes specified in C+1.
Page 435: About Sysmac Net Link/Sysmac Link Operations
Network Instructions Section 5-36 5-36-7 About SYSMAC NET Link/SYSMAC LINK Operations SEND(192), RECV(193), and CMND(194) are based on command/response processing. That is, the transmission is not complete until the sending node re- ceives and acknowledges a response from the destination node, unless the re- sponse function is disabled in the control word or data is being broadcast to all nodes in a network.
Page 436 Network Instructions Section 5-36 Port Enabled Flag 0000 A502 0128 (011) KEEP 012800 0128 0128 (030) jMOV CIO 000000 is turned ON to start transmission. CIO #000A D00000 012800 remains ON until SEND(192) has completed. (030) jMOV #0001 D00001 Data is placed into control data words to specify the 10 words to be transmitted to the PC of node 3 of network 01, through port 4, with response, 5 retries, (030)
Page 437 Network Instructions Section 5-36 Address Instruction Operands Address Instruction Operands 00000 000000 00020 A50204 00001 A50204 00021 AND NOT 012800 00002 AND NOT 012802 00022 012803 00023 KEEP(011) 012802 00003 012801 00004 KEEP(011) 012800 00024 012802 jMOV(030) 00005 012800 00025 jMOV(030) 00006 #000A...
Page 438 Network Instructions Section 5-36 Programming Example: The following program shows how to synchronize data transmission during Synchronizing Data asynchronous operation using IOSP(187) and IORS(188). In the program in PC A (the sending PC), the data is set in memory while the Enabled Flag is ON, i.e., when SEND(192) is not being executed, and a code is added in the last word of data to verify that the data has been transmitted suc- cessfully.
Page 439: Sfc Control Instructions
SFC Control Instructions Section 5-37 5-37 SFC Control Instructions SFC Control Instructions are used to control step status in the SFC program or to output transition conditions from transition programs (TOUT(202) and TCNT(123)). Refer to the CV-series PC Operation Manual: SFC for details on SFC programming.
Page 440: Pause Step: Sp(211)
SFC Control Instructions Section 5-37 Subchart Dummy Steps The specific results of executing SA(210) for steps in each step status are de- scribed below for dummy steps controlling subcharts. Execute SA(210) does not change the subchart dummy step itself. All the steps in a sub- chart that are active when SA(210) is executed go to execute status.
Page 441: Restart Step: Sr(212)
SFC Control Instructions Section 5-37 Pause, Halt, Inactive Step status does not change. Subchart Dummy Steps The specific results of executing SP(211) for steps in each step status are de- scribed below for dummy steps controlling subcharts. Execute Changes the status of the subchart dummy step from execute to pause. All ac- tive steps in the designated subchart (including those in halt status) will be placed in pause status.
Page 442: End Step: Sf(213)
SFC Control Instructions Section 5-37 5-37-4 END STEP: SF(213) Ladder Symbol Operand Data Area (213) N: Step number Variations j SF(213) Description When the execution condition is OFF, SF(213) is not executed. When the execu- tion condition is ON, SF(213) changes the status of a step or subchart from execute or pause to halt.
Page 443: Deactivate Step: Se(214)
SFC Control Instructions Section 5-37 5-37-5 DEACTIVATE STEP: SE(214) Ladder Symbol Operand Data Area (214) N: Step number Variations j SE(214) Description When the execution condition is OFF, SE(214) is not executed. When the execu- tion condition is ON, SE(214) changes the status of a step or subchart from ac- tive (execute, pause or halt) to inactive status.
Page 444: Reset Step: Soff(215)
SFC Control Instructions Section 5-37 Halt Changes status of subchart dummy step from halt to inactive, and makes inac- tive all of the steps in the subchart that were active at the time the instruction was executed. Actions will be reset. Actions with the optional hold action qualifier, however, will not be reset.
Page 445: Transition Output: Tout(202)
SFC Control Instructions Section 5-37 Pause Changes the status of the subchart dummy step from pause to inactive and places all of the steps in the subchart inactive. Execution of all actions (including actions with the optional hold action qualifier and actions with S-group AQs) will be stopped and the actions will be reset.
Page 446: Transition Counter: Tcnt(123)
SFC Control Instructions Section 5-37 If the Transition Flag turns ON, ST0000 is active (but not in pause status), and ST0010 is inactive, then all of the transition conditions are met and active status will be transferred from ST0000 to ST0010. Address Instruction Operands TN0000...
Page 447: Read Step Timer: Tsr(124)
SFC Control Instructions Section 5-37 Flags ER (A50003): ON when the content of N is not a counter number. ON when the content of S is not BCD data. On when the content of *DM or *EM word is not BCD. Example When the program for TN0020 is executed for the first time, counter C0100 will be started.
Page 448: Write Step Timer: Tsw(125)
SFC Control Instructions Section 5-37 Flags ER (A50003): ON when the N is set outside of the range. On when the content of *DM or *EM word is not BCD. Example When CIO 000000 is ON in the following example, the present value of the step timer for step ST0100 will be output to D00500 in binary data.
Page 449: Sfc Control Program Example
SFC Control Instructions Section 5-37 5-37-11 SFC Control Program Example The operation of the SFC control instructions used in the following programming example is described following the program. Action Program for AC0020 (ST0020) Main SFC Program ST0010 0130 (210) 0500 #0400 TN0010 0000...
Page 450: Block Programming Instructions
Block Programming Instructions Section 5-38 5-38 Block Programming Instructions Block programming can be used with version-2 CVM1 CPUs to program opera- tions that are difficult to program with ladder diagrams, such as certain data com- putations. Effective block programming can be use to reduce the number of pro- gramming steps required for certain operations, thus reducing the cycle time and increasing overall processing speed.
Page 451: Block Program Begin/End: Bprg(250) / Bend<001
Block Programming Instructions Section 5-38 The following instructions cannot be used in block programs. Group Mnemonic Remarks Bit control DIFU(013) instructions DIFD(014) KEEP(011) Use SET(016) and RSET(017). (There are not block SET and RSET instructions for not block SET and RSET instructions for OUT NOT CV-series PCs.) Interlock and...
Page 452: Branching-If<002>, Else<003>, And Iend<004
Block Programming Instructions Section 5-38 Precautions The same block number cannot be used more than once. Block programs cannot be nested. Example When CIO 000000 is ON in the following diagram, the block program between program addresses 000501 and 000600 will be executed. 0000 (250) Address Instruction...
Page 453 Block Programming Instructions Section 5-38 IF<002> NOT with an IF<002> NOT to ELSE to IEND Operand IF<002> NOT B When B is OFF, C is executed. ELSE<003> When B is ON, D is executed. IEND<004> IF<002> without an IF<002> to ELSE to IEND Operand LD 00000 AND 00001...
Page 454 Block Programming Instructions Section 5-38 The second block is executed when CIO 000002 is ON and shows nesting two levels. If CIO 000003 and CIO 000004 are both ON, the contents of CIO 1200 and CIO 0002 are added and the result is placed in D00010 and then 0001 is moved into D00011 based on the status of CY.
Page 455: One Cycle And Wait: Wait<005
Block Programming Instructions Section 5-38 5-38-4 ONE CYCLE AND WAIT: WAIT<005> (CVM1 V2) Ladder Symbol Operand Data Area B: Bit CIO, G, A, T, C WAIT<005> WAIT<005> WAIT<005> NOT Description WAIT<005> and WAIT<005> NOT allow you to inhibit execution of the por- tion of block program from WAIT<005>...
Page 456: Conditional Block Exit: Exit<006
Block Programming Instructions Section 5-38 The execution flow for this example would be as shown below: 000000 000001 Initial execution 000000 000001 OFF The following example would work similarly, except that execution of WAIT<005> would be based on an AND between the status of CIO 000001 and CIO 000002.
Page 457: Loop Control-Loop<009>/Lend<010
Block Programming Instructions Section 5-38 When using EXIT<006> without an bit operand, the instructions used to create the execution condition for EXIT<006> must begin with LD. Execution Flow Examples When CIO 000000 is OFF, the block program is executed as normal. If CIO 000001 turns ON, however, A is executed and then B is skipped and program control jumps to BEND<001>.
Page 458: Block Program Pause/Restart : Bpps<011>/Bprs<012
Block Programming Instructions Section 5-38 IEND<004> IEND<004> IEND<004> LEND<010> LEND<010> Loops cannot be nested within loops. Incorrect: LOOP<009> LOOP<009> LEND<010> LEND<010> Do not reverse the order of LOOP and LEND. Incorrect: LEND<010> LOOP<009> Execution Flow Examples When CIO 000000 is ON, the block program is executed. After A is executed, B and the IORF(184) after it will be executed repeatedly until CIO 000001 is ON, at which time C will be executed and the block program will end.
Page 459: High-Speed Timer/Timer Wait: Timw<013>/Tmhw<015
Block Programming Instructions Section 5-38 Example If CIO 000000 is ON, the following program suspends execution of either block program 01 or block program 02 depending on the status of CIO 000001. The block program that was suspended is then restarted after 10 seconds.
Page 460: Counter Wait: Cntw<014
Block Programming Instructions Section 5-38 Example In the following example, B will be executed 20 seconds after A whenever CIO 000000 is ON, and CIO 002000 will be set 0.2 seconds after CIO 000001 goes ON. 0000 (250) Address Instruction Operands BPRG 000000...
Page 461 Block Programming Instructions Section 5-38 Example In the following example, B will be executed after the execution of A and after 7,000 counts of CIO 000100 while CIO 000000 is ON. 0000 (250) Address Instruction Operands BPRG 000000 000000 000001 BPRG(250) CNTW<014>...
Page 462 SECTION 6 Program Execution Timing This section explains the execution cycle of the PC and shows how to calculate the cycle time and I/O response times. I/O response times in Link Systems are described in the individual System Manuals. These manuals are listed at the end of Section 1 Introduction.
Page 463: Pc Operation
PC Operation Section 6-1 PC Operation This section details basic CPU operation of CV-series PCs. The CV-series PCs can process instruction execution and I/O refreshing independently of peripheral servicing. Independent parallel processing is called asynchronous operation, and synchronized processing is called synchronous operation. Select asynchronous or synchronous operation in the PC Setup.
Page 464: Pc Operation
PC Operation Section 6-1 6-1-2 Asynchronous Operation The CV-series PCs can execute instructions and refresh I/O in parallel with peripheral servicing (CPU Bus Units, Host Link Units, etc.). Peripheral servic- ing will access data in the Link Area, SYSMAC BUS/2 Area, CPU Bus Unit Area, and CPU Bus Link Area completely independently of program execu- tion timing.
Page 465 PC Operation Section 6-1 It is possible for the data in the CPU Bus Link Area, SYSMAC BUS/2 Area, CPU Bus Unit Area, etc., to be changed by peripheral servicing between the execu- tion of two instructions or even during the execution of an instruction accessing many words.
Page 466: Synchronous Operation
PC Operation Section 6-1 6-1-3 Synchronous Operation PC operation can be set to synchronous operation in the PC Setup to syn- chronize instruction execution and peripheral servicing. The following dia- gram shows CPU operation during synchronous operation. Basic processes Basic processes CPU bus check Memory check Battery check...
Page 467 PC Operation Section 6-1 6-1-4 I/O Refreshing I/O refreshing refers to the reading of ON/OFF input bit data from Input Units to I/O memory and the writing of ON/OFF output bit data from I/O memory to Out- put Units. CPU, CPU Expansion, and Expansion I/O Racks The following list shows the five methods for refreshing I/O words allocated to Units on the CPU, CPU Expansion, and Expansion I/O Racks.
Page 468: I/O Refreshing
PC Operation Section 6-1 As shown in the following diagram, output points are refreshed (A) when the zero voltage signal is received, the program is executed (B), input points are re- freshed (C), and the CPU waits for the next zero voltage signal (D). If I/O refresh- ing and program execution exceed one half the AC cycle (B’), the next output refreshing will occur when the next zero voltage signal is received.
Page 469 PC Operation Section 6-1 SYSMAC BUS/2 I/O refreshing of Units in a SYSMAC BUS/2 System can be disabled by turning ON the corresponding CPU Bus Service Disable Bits in A015. Bits 00 to 15 correspond to Units #0 to #15, respectively. Turn the bits OFF again to enable service and resume I/O refreshing.
Page 470: Power Off Operation
PC Operation Section 6-1 3. After the power interruption signal is output, the CPU waits for the momen- tary power interruption time set in the PC Setup (default: 0 ms) before pro- ceeding. Set the power interruption time to 9–T ms max. (T is the time re- quired to execute the power OFF interrupt program if there is one), because the power maintenance time is 10 ms and 1 ms is required for the system shutdown procedure.
Page 471 PC Operation Section 6-1 Momentary Power Interruptions The following diagram and explanation show the CPU operation when the power goes off momentarily. Power interruption Power restored Power supply Power interruption detection time: 10 to 25 ms for AC power, 0.3 to 1 ms for DC power Duration of (recorded in A007) interruption...
Page 472 PC Operation Section 6-1 6-1-6 Power OFF Interruption and Restart Continuation This section details the steps required to prepare a power OFF interrupt pro- gram and to restart the PC after a power interruption. Power OFF Interrupts Power OFF Interrupt Follow the steps below to use a power OFF interrupt program.
Page 473: Power Off Interruption And Restart Continuation
PC Operation Section 6-1 Operation The diagram and explanation below describe CPU operation when the PC is set for restart continuation and power is interrupted and then returned after the CPU is stopped. Power hold time: 10 ms (fixed) Shutdown processing Momentary power (1 ms)
Page 474 PC Operation Section 6-1 4. If a power interruption occurs during initialization or execution of the power ON interrupt program, restart continuation will begin at initialization or from the beginning of the power ON interrupt program. 5. Timers are stopped when a power interruption occurs and their PVs are maintained.
Page 475: Cycle Time
Cycle Time Section 6-2 Parameters Not Maintained The following parameters are not maintained when the PC is restarted. for Restart Continuation 1, 2, 3... 1. Error status (but the Error Log is maintained.) 2. Disabled access to I/O memory by IOSP(187) 3.
Page 476: Cycle Time
Cycle Time Section 6-2 Instruction Execution Cycle Time Process Actions Processing time CV500/CVM1-CPU01-EV2 CV1000/2000/ CVM1-CPU11/21-EV2 Basic Checks the cycle time and PC memory. 0.6 ms 0.5 ms processes Event Execution of non-scheduled requests for 0 ms if there is no processing request; 20 ms max. processing data processing from peripherals.
Page 477 Cycle Time Section 6-2 Peripheral Servicing Cycle Time Processes Actions Processing time CV500/CVM1-CPU01-EV2 CV1000/2000/ CVM1-CPU11/21-EV2 Basic Checks the CPU bus, PC memory, Approx. 2.8 ms processes battery, start input, and updates the clock. CPU Bus Unit Starting from Unit #0, events (requests for Approx.
Page 478: Synchronous Operation
Cycle Time Section 6-2 6-2-2 Synchronous Operation In synchronous operation, instruction execution and I/O refreshing are pro- cessed along with peripheral servicing (CPU Bus Units, host interface, etc.) in a single cycle. The cycle time is thus the sum of the time required for instruction execution and that required for peripheral servicing, and the cycle time will lengthen as more peripherals are connected.
Page 479 Cycle Time Section 6-2 Interrupt Processing Depending on the program, the following interrupt processes might be executed in addition to the processes detailed in the table above. The actual cycle time is the sum of the cycle time calculated in the table above and the time required for the processes in the table below.
Page 480: Operations Significantly Increasing Cycle Time
Cycle Time Section 6-2 Note 1. In the earlier version, executing the online edit operation could increase cycle time by as much as 3 seconds. In the CVM1(V2), PC operation is stopped for the times shown in the following table but there is no effect on cycle time (i.e., those times are not added to the cycle time).
Page 481: Calculating Cycle Time
Calculating Cycle Time Section 6-3 The following CVSS/SSS operations are instruction execution events: Monitoring, data modification, set, reset, online edit, DM edit, search, transfer block (CVSS/SSS to PC), save block (CVSS/SSS to PC), I/O table change, PC Setup, PC Setup information transfer, data trace execution, program trace execution, setting program memory protect, clearing program memory protect, Memory Card (program, I/O memory) The following host interface operations are writing events:...
Page 482: Calculating Cycle Time
Calculating Cycle Time Section 6-3 The output refreshing time would be as follows for the five 16-point Output Units and six 32-point Output Units controlled by the PC: (16 points x 5) + (32 points x 6) x 7 µs = 0.12 ms 16 points The input refresh time would be as follows for the five 16-point Input Units and five 32-point Input Units controlled by the PC:...
Page 483: Instruction Execution Times
Instruction Execution Times Section 6-4 Instruction Execution Times This following table lists the execution times for CV-series PC instructions. The maximum and minimum execution times and the conditions which cause them are given where relevant. When “word” is referred to in the Conditions column, it implies the content of any word except for indirectly addressed DM words.
Page 484: Instruction Execution Times
Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* OR NOT CIO 000000 to CIO 051115 for 0.15 0.13 0.15 0.13 operand CIO 051200 to CIO 255515 for 0.25 0.25 j/i: 0.45...
Page 485 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* !CMP(020) Additional time over CMP(020) for +5.5 +5.0 1.05 0.88 each input word being compared Additional time over CMP(020) for +4.4 +4.0 each output word being compared...
Page 486 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* MVNL(033) When transferring a word to a word When transferring *DM to *DM XCHG(034) Word word XCGL(035) Word word 10.2 10.8...
Page 487 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* WSFT(053) When shifting 1 word 13.8 11.5 1.35 1.13 When shifting 1000 DM words using 1.40 ms 1.17 ms NSFL(054) Shifting 1 bit in a word 18.9...
Page 488 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* 25.4 21.1 ADDL(074) Constant + word word 21.8 18.0 1.35 1.13 *DM + *DM 25.8 21.5 SUBL(075) Constant – word word 21.0 17.5...
Page 489 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* When converting *DM to *DM BINL(102) When converting a word to a word 10.2 When converting *DM to *DM 12.6 10.5 BCDL(103)
Page 490 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* XORW(132) Constant XOR word word *DM XOR *DM 11.1 XNRW(133) Constant XNOR word word 1.35 1.13 *DM XNOR *DM 11.1 ANDL(134) Constant AND word...
Page 491 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* SRCH(164) When searching 1 word 1.35 1.13 When searching 1000 words for *DM 11.4 ms 9.54 ms MAX(165) When searching 1 word 1.35 1.13...
Page 492 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* SA(210) When activating 1 step 39.5 32.9 When activating a 15-step subchart 48.2 40.1 SP(211) When pausing 1 step 25.8 21.5 1.05...
Page 493 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* Reading 255 words *DM to *DM 26.0 21.6 WR2(281) Writing 1 word to word 21.3 17.8 5.40 4.50 Writing 255 words *DM to *DM 27.0 22.5...
Page 494 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* >=S(327) Comparing constant and word 15.0 12.5 6.15 5.13 Comparing *DM and *DM 20.4 17.0 >=SL(328) Comparing constant and word 15.9 13.3 Comparing *DM and *DM...
Page 495 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* Constant x word word 46.8 39.0 1.35 1.13 * UL(423) *DM x *DM 54.0 45.0 Constant x word word 22.1 18.4...
Page 496 Instruction Execution Times Section 6-4 µ µ Instruction Words Conditions ON execution time ( OFF execution time ( CV500* CV1000* CV500* CV1000* IF<002> Without operand 4.20 3.50 2.70 2.25 With operand 8.10 6.75 ELSE<003> 4.35 3.63 IEND<004> 4.50 3.75 WAIT<005> Without operand 4.35 3.63...
Page 497: I/O Response Time
I/O Response Time Section 6-5 I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the input re- fresh period.
Page 498: I/O Response Time
I/O Response Time Section 6-5 Maximum I/O Response The PC takes longest to respond when it receives the input signal just after the Time input refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time.
Page 499 I/O Response Time Section 6-5 Minimum I/O Response The PC responds most quickly when the instruction that uses the input signal is Time executed between two SYSMAC BUS refreshes. This situation is illustrated be- low. Cycle time Program execution Cycle I/O refresh Buffer in Master 5 ms...
Page 500 I/O Response Time Section 6-5 Maximum I/O response time = 1.5 + (20 + 10) + (8.2 2) + 2.2 + 15 = 65.1 ms 6-5-3 Synchronous Operation with a SYSMAC BUS System Here, we’ll compute the minimum and maximum I/O response times for a CV1000 that is set for synchronous operation and controls a SYSMAC BUS Sys- tem.
Page 501: Synchronous Operation With A Sysmac Bus System
I/O Response Time Section 6-5 Maximum I/O Response The PC takes longest to respond when the Master receives the input signal just Time after I/O refreshing. This situation is illustrated below. Cycle time Cycle A: Program execution B: Peripheral servicing I/O refresh Buffer in Master Transmission time...
Page 502 I/O Response Time Section 6-5 The remote refresh time is 2.0 + (0.2 a ) ms, where a is the number of words to refresh. The communications cycle time is 5 ms or the sum total of the commu- nications times of Slaves connected to the Master. The communications cycle time can also be set in the SYSMAC BUS/2 settings in the PC Setup, refer to the SYSMAC BUS/2 Remote I/O System Manual for details.
Page 503: Synchronous Operation With A Sysmac Bus/2 System
I/O Response Time Section 6-5 Maximum I/O Response The PC takes longest to respond when the relevant instruction is executed just Time prior to SYSMAC BUS/2 refreshing. In this case the CPU does not execute the instruction with the new input bit status until the next cycle. This situation is illus- trated below.
Page 504 I/O Response Time Section 6-5 Minimum I/O Response The PC responds most quickly when it receives an input signal just prior to SYS- Time MAC BUS/2 refreshing. Cycle time A: Program execution Cycle B: Peripheral servicing I/O refresh Buffer in Master Input signal Input ON delay Output ON delay...
Page 505: Pc Setup
SECTION 7 PC Setup The tables in this section list the parameters in the PC Setup, provide examples of normal application, and provide the default values. The PC Setup can be changed from the CVSS/SSS. Refer to CVSS/SSS Operation Manuals for details changing set- tings.
Page 506: Pc Setup Overview
PC Setup Overview Section 7-1 PC Setup Overview Parameter Function Normal application(s) A:Hold areas H:Hold areas Specifies which bits are to maintain To extend the Holding Area beyond CIO status when power is turned off. 300. R:Hold bits Specifies Racks or Masters (Remote To maintain output status for specific I/O Subsystems) that are to maintain Racks or Remote I/O Subsystems.
Page 507: Pc Setup Details
PC Setup Details Section 7-2 Parameter Function Normal application(s) J:Scheduled interrupt Sets the unit for setting the scheduled interrupt to 10.0, 1.0, or 0.5 ms. K:1st Rack addr Sets the first word for each of the CPU, To simplify word allocations, to prevent Expansion CPU, and Expansion I/O changes in allocations, or to allow for Racks.
Page 508 PC Setup Details Section 7-2 Name Operation B:Startup Forced Status Hold Specify whether the status of the Forced Status Hold Bit is to be maintained or hold Bit status (A00013) reset to OFF when power is turned on. If A00013 is reset, the forced ON/OFF (Forced status) status of all force-set and force-reset bits will be cleared when power is turned on.
Page 509 PC Setup Details Section 7-2 Name Operation F:Execute Detect low battery Designate whether battery errors are detected. Changes to this setting are control 1 effective immediately. (Default: Detect) The following bits will be turned ON when a battery error is detected. A40204 Battery Low Flag (PC or Memory Card) A42614 Memory Card Battery Low Flag A42615 PC Battery Low Flag...
Page 510 PC Setup Details Section 7-2 Name Operation H:Host link Baud rate Designate 1200, 2400, 4800, 9600, or 19200 bps. (Default: 9600 bps) Stop bits Designate either 1 stop bit or 2 stop bits. (Default: 2 stop bits) Parity Designate even, odd, or no parity. (Default: Even parity) Data length Designate either 7-bit or 8-bit data.
Page 511: Pc Setup Default Settings
PC Setup Default Settings Section 7-3 Name Operation P:Power break Designate the momentary power interruption time between 0 and 9 ms. Operation will continue for momentary power interruptions if the power supply is restored within this time after a power interruption. If the momentary power interruption time is greater than 0 ms, Peripheral Device and Host Link communications may be disrupted and may go on standby for momentary power interruptions.
Page 512 PC Setup Default Settings Section 7-3 Parameter Default value G:Execute C:Execute process Asynchronous control 2 I:I/O interrupt Nesting D:Power OFF interrupt Disable A:Dup action process Error T:Step timer Set to 0.1 s J:Startup trace Don’t start trace. B:*DM BIN/BCD P:Multiple use of JMP000 Enabled E:Compare error process Run after error...
Page 513: Error Processing
SECTION 8 Error Processing This section provides information on hardware and software errors that occur during PC operation. Program input and program syntax errors are described in the CVSS/SSS Operation Manuals. Although described in Section 3 Memory Areas, flags and other error information provided in the Auxiliary Area are listed in 8-5 Error Flags. Alarm Indicators .
Page 514: Alarm Indicators
Error Messages Section 8-4 Alarm Indicators There are two indicators on the front of the CPU that provide visual indication of an abnormality in the PC. The error indicator (ERROR) indicates fatal er- rors (i.e., ones that will stop PC operation); the alarm indicator (ALARM) indi- cates non-fatal ones.
Page 515: Initialization Errors
Error Messages Section 8-4 The Error Log contains a record the last 100 errors and can be expanded in the PC Setup to record up to 2,047 errors. Each record stores the error code, the error contents (for example the SFC error code for an SFC error), and the date and time that the error occurred.
Page 516: Error Messages
Error Messages Section 8-4 Error Probable cause Flag(s) Error code Possible remedy (A400) I/O table error Unit has been removed making A40209 00E7 Check the I/O table from the I/O table incorrect. CVSS/SSS and either connect Dummy I/O Units or correct the I/O table.
Page 517: Non-Fatal Operating Errors
Error Messages Section 8-4 8-4-3 Fatal Operating Errors The following errors occur after program execution has been started. PC opera- tion and program execution will stop and all outputs from the PC will be turned OFF when any of the following errors occur. None of the CPU indicators will be lit for the power interruption error, and only the POWER indicator will be lit for the Expansion Rack power interruption error.
Page 518 Error Messages Section 8-4 Error and message Probable Cause Flag(s) Error code Possible remedy (A400) Cycle time too long The cycle time has A40108 809F Change the program or the exceeded the maximum maximum cycle time. cycle time set in the PC Setup.
Page 519: Error Flags
Error Flags Section 8-5 Error Flags The following table lists the flags and other information provided in the Auxil- iary Area that can be used in troubleshooting. Details are provided in 3-6 Auxiliary Area. Fatal Errors Error Address(es) Function Power interruption error A012 and A013 Date and time of last power interruption...
Page 520: Error Flags
Error Flags Section 8-5 Error Address(es) Function SYSMAC BUS error A40205 SYSMAC BUS Error Flag A425 SYSMAC BUS error Master number A470 to A477 Slave unit number Battery error A40204 Battery Low Flag A42614 Memory Card Battery Low Flag A42615 PC Battery Low Flag CPU Bus Unit setting error A40203 CPU Bus Unit Parameter Error Flag...
Page 521: A Instruction Set
Appendix A Instruction Set Alphabetic List of Instructions by Mnemonics The DM and EM areas can be indirectly addressed by specifying the data area as *DM or *EM, and then entering the address of the DM or EM word that contains the actual data. Index and data registers can also be used for indirect addressing.
Page 522 Instruction Set Appendix A Mnemonic Code Name Mnemonic Code Name LEND(NOT) <010> REPEAT BLOCK END 16-TO-4/256-8 ENCODER DMPX(j) DOWN* CONDITION OFF LIFO(j) LAST IN FIRST OUT DVB(j) BINARY DIVIDE LINE(j) COLUMN-TO-LINE DVBL(j) DOUBLE BINARY DIVIDE LMT(j)* LIMIT CONTROL ELSE* <003> NO CONDITIONAL BRANCH LOGARITHM LOG(j)*...
Page 523 Instruction Set Appendix A Mnemonic Code Name Mnemonic Code Name RAD(j)* DEGREES-TO-RADIANS SQUARE ROOT SQRT(j)* RD2* I/O READ 2 SR(j) RESTART STEP READ I/O READ DATA SEARCH SRCH(j) RECV(j) NETWORK RECEIVE SRD(j) SHIFT DIGIT RIGHT REGL(j) LOAD REGISTER SSET(j) SET STACK SAVE REGISTER REGS(j) STC(j)
Page 524 Instruction Set Appendix A Mnemonic Code Name Mnemonic Code Name SIGNED EQUAL /F(j)* FLOATING-POINT DIVIDE =SL* DOUBLE SIGNED EQUAL /L(j)* DOUBLE SIGNED BINARY DIVIDE <* LESS THAN /U(j)* UNSIGNED BINARY DIVIDE <=* LESS THAN OR EQUAL /UL(j)* DOUBLE UNSIGNED BINARY <=L* DOUBLE LESS THAN OR DIVIDE...
Page 525 Instruction Set Appendix A Alphabetic List of Instructions by Function Code Sequence Control, Error Handling, and Step Data Move and Sequence Output Instructions Control Instructions Code Mnemonic Name Code Mnemonic Name MOV(!j) MOVE NO OPERATION MVN(j) MOVE NOT MOVL(j) DOUBLE MOVE INTERLOCK MVNL(j) DOUBLE MOVE NOT...
Page 526 Instruction Set Appendix A Data Shift Instructions Binary Calculation Instructions Code Mnemonic Name Code Mnemonic Name BINARY ADD ADB(j) SHIFT REGISTER SBB(j) BINARY SUBTRACT REVERSIBLE SHIFT SFTR(j) REGISTER MLB(j) BINARY MULTIPLY ASFT(j) ASYNCHRONOUS SHIFT DVB(j) BINARY DIVIDE REGISTER DOUBLE BINARY ADD ADBL(j) WSFT(j) WORD SHIFT...
Page 527 Instruction Set Appendix A Special Timer and SFC Control Instructions Table Data Processing Instructions Code Mnemonic Name Code Mnemonic Name SSET(j) SET STACK TTIM ACCUMULATIVE TIMER PUSH ONTO STACK PUSH(j) TIML DOUBLE TIMER LIFO(j) LAST IN FIRST OUT MTIM MULTI-OUTPUT TIMER FIFO(j) FIRST IN FIRST OUT TCNT...
Page 528 Instruction Set Appendix A SFC Control Instructions Data Control, Special Calculation, and Data Conversion Instructions Code Mnemonic Name Code Mnemonic Name TOUT TRANSITION OUTPUT PID* PID CONTROL SA(j) ACTIVATE STEP LIMIT CONTROL LMT(j)* PAUSE STEP SP(j) BAND(j)* DEAD BAND CONTROL SR(j) RESTART STEP ZONE(j)*...
Page 529 Instruction Set Appendix A Bit Tests Floating-point Math Instructions Code Mnemonic Name Code Mnemonic Name TST* BIT TEST FIX(j)* FLOATING-TO-16-BIT TSTN* BIT TEST FLOATING-TO-32-BIT FIXL(j)* FLT(j)* 16-BIT-TO-FLOATING Symbol Math Instructions FLTL(j)* 32-BIT-TO-FLOATING Code Mnemonic Name +F(j)* FLOATING-POINT ADD SIGNED BINARY ADD +(j)* WITHOUT CARRY FLOATING-POINT...
Page 530 Instruction Set Appendix A Programming Instructions The following tables detail all of the ladder diagram programming instructions for the CV-series PCs and the applicable data areas for each. Bit and word addresses for each area are given in the footnotes. Up and down differentiated instructions are indicated with an up or down arrow (j or i) prefix.
Page 531 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas Logically ORs the status of the designated bit OR, !OR, jOR, iOR, with the current execution condition. !jOR, !iOR OR NOT Logically ORs the inverse of the status of the OR NOT, !OR NOT designated bit with the current execution condition.
Page 532 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas COUNTER Creates a decrementing counter. S (set value): 0 to 9999; CP: count pulse; R: reset input. Each counter number (BCD) can be used in only one counter instruction (CNT, CNTR(012), and TCNT(123)), unless the counters are never active simultaneously.
Page 533 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas FAILURE ALARM Outputs a FAL error number (N) and FAL, jFAL generates a non-fatal error when the execution condition is ON. N must be between 001 and 511. When the FAL number is (006) generated, a corresponding bit is turned ON in the FAL output area, and the FAL number is...
Page 534 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DIFFERENTIATE UP DIFU(013) turns ON the designated bit (B) for DIFU, !DIFU one cycle when the execution condition changes from OFF to ON. (013) DIFU DIFFERENTIATE DOWN DIFD(014) turns ON the designated bit (B) for DIFD, !DIFD one cycle when the execution condition...
Page 535 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas BLOCK COMPARE Compares a 1-word binary value (S) with the BCMP, jBCMP 16 ranges given in the comparison table (CB is the starting word of the comparison block). If the value falls within any of the ranges, the (022) corresponding bits in the result word (R) is...
Page 536 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas EQUAL Compares the data in two 4-digit hexadecimal EQU, jEQU words (Cp and Cp ) and produces an ON execution condition if the contents are the same.
Page 537 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE MOVE Copies data from the source words (S and MOVL, jMOVL S+1) to the destination words (D and D+1). (032) MOVl DOUBLE MOVE NOT Copies the inverse of the data in the source MVNL, jMVNL words (S and S+1) to destination words (D and D+1).
Page 538 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas BLOCK TRANSFER Moves the content of several consecutive XFER, jXFER source words (S gives the address of the starting source word) to consecutive destination words (D is the starting destination (040) word).
Page 539 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SINGLE WORD DISTRIBUTE Copies one word of source data (S) to the DBs: DIST, jDIST destination word whose address is given by the destination base word (DBs) plus the offset (Of).
Page 540 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas REVERSIBLE SHIFT REGISTER Shifts bits in the specified word or series of SFTR, jSFTR words either left or right. Starting (St) and ending words (E) must be specified. Control word (C) contains shift direction, reset input, (051) and data input.
Page 541 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SHIFT N-BIT DATA RIGHT (V2 only) Shifts the specified number of bits (i.e., the NSFR, NSFR shift data length), from the beginning bit of the beginning word, one bit at a time to the right. A “0”...
Page 542 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas ARITHMETIC SHIFT LEFT Each bit within a single word of data (Wd) is ASL, jASL shifted one bit to the left, with zero written to bit 00 and bit 15 moved to CY. (060) ARITHMETIC SHIFT RIGHT Each bit within a single word of data (Wd) is...
Page 543 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SHIFT DIGIT LEFT Shifts all data between the starting word (St) SLD, jSLD and ending word (E) one digit (four bits) to the left, writing zero into the rightmost digit of the starting word.
Page 544 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas BCD DIVIDE Divides the 4-digit BCD dividend (Dd) by the DIV, jDIV 4-digit BCD divisor (Dr) and outputs the result to the specified result words. R receives the quotient;...
Page 545 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas CLEAR CARRY Clears the Carry Flag (i.e., turns OFF None CLC, jCLC A50004). (079) BINARY ADD Adds two 4-digit hexadecimal values (Au and ADB, jADB Ad) and content of CY and outputs the result to the specified result word (R).
Page 546 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE BINARY SUBTRACT Subtracts both the 8-digit hexadecimal SBBL, jSBBL subtrahend and the content of CY from an 8-digit hexadecimal minuend and outputs the result to the specified result words. All words (085) for any one operand must be in the same data SBBL...
Page 547 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DECREMENT BINARY Decrements the value of a 4-digit hexadecimal DECB, jDECB word (Wd) by one, without affecting carry (CY). (093) DECB DOUBLE INCREMENT BCD Increments the 8-digit BCD value contained in INCL, jINCL Wd+1 and Wd, without affecting carry (CY).
Page 548 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE BCD-TO-DOUBLE BINARY Converts the BCD value of the two source BINL, jBINL words (S: starting word) into binary and outputs the converted data to the two result words (R: starting word).
Page 549 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DATA DECODER Converts up to four hexadecimal digits in the MLPX, jMLPX source word (S) into decimal values from 0 to 15 and turns ON the corresponding bit(s) in the result word(s) (R), or converts up to two (110) 8-bit values in the source word (S) into...
Page 550 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas ASCII CONVERT Converts hexadecimal digits from the source ASC, jASC word (S) into 8-bit ASCII values, starting at leftmost or rightmost half of the starting destination word (D). The rightmost digit of Di (113) designates the first source digit.
Page 551 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas ASCII TO HEX (V2 only) Converts the data in specified words from HEX, HEX ASCII to hexadecimal, and outputs the result to a specified destination word. MSB LSB (117) Specifies the first digit to be output.
Page 552 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas TRANSITION COUNTER Computes the number of times that a TCNT transition program is executed and turns ON the Transition Flag when the preset count is reached. Each counter number (BCD) can be (123) used in only one counter instruction (CNT, TCNT...
Page 553 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE LOGICAL AND Logically ANDs the contents of I and I ANDL, jANDL with the contents of I and I +1 and sets the bits in the result words (R and R+1) if the corresponding bits in the input words are both (134) ANDL...
Page 554 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas FLOATING POINT DIVIDE Divides one floating point value by another FDIV, jFDIV and outputs a floating point result. The rightmost seven digits of each set of two words (eight digits) are used for mantissa, and (141) the leftmost digit is used for the exponent and...
Page 555 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SUBROUTINE ENTRY Calls subroutine N. Moves program operation to the specified subroutine. N must be BCD between 000 and 999 for the CV1000, (150) CV2000, or CVM1-CPU11/21-EV2 or between 000 and 099 for the CV500 or CVM1-CPU01-EV2.
Page 556 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SET STACK Defines a stack from TB to TB+N–1 and SSET, jSSET resets to zero all words from TB+2 to TB+N–1. TB contains the memory address for TB+N–1, and TB+1 contains the memory address of (160) TB+2.
Page 557 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas FIND MINIMUM Searches the range of memory from St to MIN, jMIN St+N–1 for the address that contains the minimum value and outputs that value to the destination word (D).
Page 558 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SAVE REGISTER Copies the data from Data Registers DR0, REGS, jREGS DR1, and DR2 to D, D+1, and D+2, and copies the data from Index Registers IR0, IR1, and IR2 to D+3, D+4, and D+5.
Page 559 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas CHANGE STEP PROGRAM Reads from the Memory Card the action block FLSP, jFLSP in the step program file (extension .SFC) specified in C and replaces the action block for step N with it.
Page 560 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas I/O READ Reads data from memory area of a Special I/O READ Unit through a word (S) allocated to the Special I/O Unit to destination words (D gives the address of the first destination word).
Page 561 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas NETWORK RECEIVE Receives data from n source words (S is the S/D/C: RECV, jRECV starting word) from the specified node of the specified network and writes it to the destination words (D is the first word) in a (193) SYSMAC LINK or SYSMAC NET Link System.
Page 562 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas PAUSE STEP Changes a step or subchart from execute to SP, jSP pause status. To pause a subchart, specify the subchart dummy step for N . Actions with S-type action qualifiers will continue to be (211) executed.
Page 563 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas BLOCK PROGRAM (V2 only) Indicates the beginning of the designated BPRG block program. (250) BPRG ROTATE LEFT WITHOUT (V2 only) Shifts all Wd bits one bit to the left, shifting the CARRY status of bit 15 of Wd simultaneously into bit RLNC, RLNC...
Page 564 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DEAD-ZONE CONTROL (V2 only) Adds the specified bias value to the specified ZONE, ZONE input data (signed 16-bit binary) and places the result in a specified word. (273) ZONE BINARY ROOT...
Page 565 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas I/O WRITE 2 (V2 only) Writes the specified number of words to a WR2, WR2 specified address in a Special I/O Unit, via a specified Special I/O Unit interface word (S) in the PC’s memory.
Page 566 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE SIGNED NOT (V2 only) Compares word data and constants in eight EQUAL digits signed hexadecimal, and turns ON the < >SL execution condition if the result is true (i.e., if <>...
Page 567 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SIGNED LESS THAN OR (V2 only) Compares word data and constants in four EQUAL digits signed hexadecimal, and turns ON the < =S execution condition if the result is true (i.e., if (317) <=S DOUBLE SIGNED LESS...
Page 568 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE GREATER THAN OR (V2 only) Compares word data and constants in eight EQUAL digits hexadecimal, and turns ON the > =L execution condition if the result is true (i.e., if (326) >=L SIGNED GREATER THAN OR...
Page 569 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas SIGNED BINARY ADD WITH (V2 only) Adds word data and constants, including carry, CARRY in four digits hexadecimal with sign, and outputs the result to a specified word. (402) DOUBLE SIGNED BINARY (V2 only) Adds word data and constants, including carry,...
Page 570 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE BCD ADD WITH (V2 only) Adds word data and constants, including carry, CARRY in eight digits BCD, and outputs the result to +BCL, +BCL specified words. (407) Au+1 +BCL...
Page 571 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas BCD SUBTRACT WITHOUT (V2 only) Subtracts word data and constants in four CARRY digits BCD, and outputs the result to a –B, –B specified word. (414) –B –...
Page 572 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE SIGNED BINARY (V2 only) Multiplies word data and constants in eight MULTIPLY digits hexadecimal with sign, and outputs the * L, result to specified words. (421) Md+1 Mr + 1...
Page 573 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DOUBLE SIGNED BINARY (V2 only) Divides word data and constants in eight digits DIVIDE hexadecimal with sign, and outputs the result to specified words. Dd+1 (431) Dr + 1 R + 3 R+ 2...
Page 574 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas FLOATING TO 32-BIT (V2 only) Converts specified 32-bit floating-point data to FIXL, FIXL 32-bit binary data, and places the result in a specified word. (451) FIXL 16-BIT TO FLOATING (V2 only) Converts specified 16-bit binary data to 32-bit FLT, FLT...
Page 575 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas DEGREES TO RADIANS (V2 only) Converts specified 32-bit floating-point data RAD, RAD from degrees to radians, and places the result in specified words. (458) RADIANS TO DEGREES (V2 only) Converts specified 32-bit floating-point data DEG, DEG from radians to degrees, and places the result...
Page 576 Instruction Set Appendix A Name, mnemonic, variations, Function Operand data Page and symbol areas EXPONENT (V2 only) Computes the exponent for specified 32-bit EXP, EXP floating-point data, and places the result in specified words. (467) LOGARITHM (V2 only) Computes the natural logarithm for specified LOG, LOG 32-bit floating-point data, and places the result in specified words.
Page 577 Instruction Set Appendix A Block Programming Instructions The following instructions are supported by version-2 CVM1 CPUs only. Name Mnemonic Function Operand Data Areas Page BLOCK PROGRAM END Indicates the end of a block program. None BEND<001> CONDITIONAL BRANCH Indicates the part of the program that is to be executed IF<002>...
Page 578 Instruction Set Appendix A Name Mnemonic Function Operand Data Areas Page HIGH-SPEED TIMER The portion of program between the TIMH<015> WAIT instruction and BEND<004> is not executed until the set TMHW<015> N value of the high-speed timer has been reached. SV: 00.00 to 99.99 s...
Page 579: B Error And Arithmetic Flag Operation
Appendix B Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY, GR, LE, EQ, OF, UF, and N flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GR indicates that a compared value is larger than some standard, LE that it is smaller, EQ that it is the same.
Page 580 Error and Arithmetic Flag Operation Appendix B Instructions A50003 A50004 A50005 A50006 A50007 A50008 A50009 A50010 (ER) (CY) (GR) (EQ) (LE) (OF) (UF) MOV(030) ON/OFF ON/OFF ON/OFF MVN(031) MOVL(032) MVNL(033) XCHG(034) ON/OFF XCGL(035) MOVR(036) ON/OFF ON/OFF XFRB(038)* ON/OFF ON/OFF XFER(040) BSET(041) MOVB(042) MOVD(043)
Page 581 Error and Arithmetic Flag Operation Appendix B Instructions A50003 A50004 A50005 A50006 A50007 A50008 A50009 A50010 (ER) (CY) (GR) (EQ) (LE) (OF) (UF) ADB(080) ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF SBB(081) MLB(082) ON/OFF ON/OFF ON/OFF DVB(083) ADBL(084) ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF...
Page 582 Error and Arithmetic Flag Operation Appendix B Instructions A50003 A50004 A50005 A50006 A50007 A50008 A50009 A50010 (ER) (CY) (GR) (EQ) (LE) (OF) (UF) ROOT(140) ON/OFF ON/OFF FDIV(141) APR(142) ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF SEC(143) HMS(144) CADD(145) CSUB(146) SBS(151) ON/OFF MSKS(153) CLI(154) MSKR(155) MCRO(156)*...
Page 583 Error and Arithmetic Flag Operation Appendix B Instructions A50003 A50004 A50005 A50006 A50007 A50008 A50009 A50010 (ER) (CY) (GR) (EQ) (LE) (OF) (UF) LMT(271)* ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF BAND(272)* ZONE(273)* ROTB(274)* ON/OFF ON/OFF ON/OFF BINS(275)* ON/OFF ON/OFF ON/OFF BCDS(276)* BISL(277)* BDSL(278)* ON/OFF...
Page 584 Error and Arithmetic Flag Operation Appendix B Instructions A50003 A50004 A50005 A50006 A50007 A50008 A50009 A50010 (ER) (CY) (GR) (EQ) (LE) (OF) (UF) SIN(460)* ON/OFF ON/OFF ON/OFF COS(461)* TAN(462)* ON/OFF ON/OFF ON/OFF ON/OFF ASIN(463)* ON/OFF ON/OFF ON/OFF ACOS(464)* ON/OFF ON/OFF ATAN(465)* ON/OFF ON/OFF...
Page 585: C Pc Setup Default Settings
Appendix C PC Setup Default Settings Parameter Default value A:Hold areas H:Hold areas CIO 1200 to CIO 1499 R:Hold bits Nothing held. B:Startup hold K:Forced Status Reset at startup. I:I/O bits D:Power on flag C:Startup mode PROGRAM D:Startup processing Don’t transfer program. E:I/O refresh Cyclic refreshing F:Execute...
Page 586 PC Setup Default Settings Appendix C Parameter Default value S:Error log 20 records in A100 through A199 T:IOIF, RT display (Slave display modes at Mode 1 startup)
Page 587: D Data Areas
Appendix D Data Areas The data areas in the CV-series PCs are summarized below. These are the same for all PCs unless specified. Only dedicated bits are shown specifically. The use of all other bits is determined either by the System the PC is involved in, e.g., SYSMAC LINK Systems use the Link Area, or by the programmer, e.g., storage of data in the Dm Area.
Page 588 Data Areas Appendix D Dedicated Bits Some of the bits in the CPU Bus Link Area and most of the bits in the Auxiliary Area and are dedicated for specific purposes. These are summarized in the following tables. Refer to 3-5 CPU Bus Link Area and 3-6 Auxiliary Area for details.
Page 589 Data Areas Appendix D Auxiliary Area As a rule, Auxiliary Area bits can be used only for the purposes for which they are dedicated. A256 to A511 are read only. Word(s) Bit(s) Function A000 00 to 10 Not used. Restart Continuation Bit IOM Hold Bit Forced Status Hold Bit Error Log Reset Bit...
Page 590 Data Areas Appendix D Word(s) Bit(s) Function A302 00 to 15 CPU Bus Unit Initializing Flags A303 to A305 00 to 15 Not used. A306 Start Input Wait Flag I/O Verification Error Wait Flag SYSMAC BUS Terminator Wait Flag CPU Bus Unit Initializing Wait Flag 04 to 07 Not used.
Page 591 Data Areas Appendix D Word(s) Bit(s) Function A402 00 to 01 Not used. Power Interruption Flag CPU Bus Unit Setting Error Flag Battery Low Flag SYSMAC BUS Error Flag SYSMAC BUS/2 Error Flag CPU Bus Unit Error Flag Not used. I/O Verification Error Flag Not used.
Page 592 Data Areas Appendix D Word(s) Bit(s) Function A462 to A463 00 to 15 Maximum Cycle Time (BCD, 8 digits) A464 to A465 00 to 15 Present Cycle Time (BCD, 8 digits) A466 to A469 00 to 15 Not used. A470 to A477 00 to 15 SYSMAC BUS Error Codes: RM # 0 (A470)
Page 593: E I/O Assignment Sheets
Appendix E I/O Assignment Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments on the Racks, as well as details of work bits, data storage areas, timers, and counters.
Page 594 I/O Bits I/O Assignment Sheets Appendix E Programmer: Program: Date: Page: Word: Unit: Word: Unit: Field device Notes Field device Notes Word: Unit: Word: Unit: Field device Notes Field device Notes...
Page 595 Work Bits I/O Assignment Sheets Appendix E Programmer: Program: Date: Page: Area: Word: Area: Word: Usage Notes Usage Notes Area: Word: Area: Word: Usage Notes Usage Notes...
Page 596 Data Storage I/O Assignment Sheets Appendix E Programmer: Program: Date: Page: Word Contents Notes Word Contents Notes...
Page 597 Timers and Counters I/O Assignment Sheets Appendix E Programmer: Program: Date: Page: Timer Set value Notes Counter Set value Notes...
Page 598: F Program Coding Sheet
Appendix F Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, al- lowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands.
Page 599 Program Coding Sheet Appendix F Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s)
Page 600 Program Coding Sheet Appendix F Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s)
Page 601: G Data Conversion Table
Appendix G Data Conversion Table Decimal Binary 00000000 00000000 00000001 00000001 00000010 00000010 00000011 00000011 00000100 00000100 00000101 00000101 00000110 00000110 00000111 00000111 00001000 00001000 00001001 00001001 00010000 00001010 00010001 00001011 00010010 00001100 00010011 00001101 00010100 00001110 00010101 00001111 00010110 00010000 00010111 00010001...
Page 602: H Extended Ascii
Appendix H Extended ASCII Bits 0 to 3 Bits 4 to 7 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0000 Space 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110...
Page 603: Glossary
Glossary action In SFC programs, the individual executable elements in an action block. An ac- tion can be defined either as a ladder diagram or as a single bit in memory. Action Area A memory area that contains flags that indicate when actions are active. action block A collection of all the actions for a single step in an SFC program.
Page 604 Glossary ASCII Short for American Standard Code for Information Interchange. ASCII is used to code characters for output to printers and other external devices. asynchronous execution Execution of programs and servicing operations in which program execution and servicing are not synchronized with each other. auto-decrement A process that can be used when addressing memory through index registers so that the address in the register is automatically reduced by 1 before each use.
Page 605 Glossary and OFF. A bit represents one binary digit. Some bits at particular addresses are allocated to special purposes, such as holding the status of input from external devices, while other bits are available for general use in programming. bit address The location in memory where a bit of data is stored.
Page 606 Glossary clock pulse A pulse available at specific bits in memory for use in timing operations. Various clock pulses are available with different pulse widths, and therefore different fre- quencies. clock pulse bit A bit in memory that supplies a pulse that can be used to time operations. Vari- ous clock pulse bits are available with different pulse widths, and therefore differ- ent frequencies.
Page 607 Glossary C-series PC Any of the following PCs: C2000H, C1000H, C500, C200H, C40H, C28H, C20H, C60K, C60P, C40K, C40P, C28K, C28P, C20K, C20P, C120, or C20. custom data area A data area defined by the user within the CIO Area. Custom data areas can be set from the CVSS and certain other Programming Devices.
Page 608 Glossary definer A number used as an operand for an instruction but that serves to define the in- struction itself, rather that the data on which the instruction is to operate. Defin- ers include jump numbers, subroutine numbers, etc. destination The location where an instruction places the data on which it is operating, as op- posed to the location from which data is taken for use in the instruction.
Page 609 Glossary DM Area. Area addresses are prefixes with E and only words can be accessed. The EM Area is separated into multiple banks. EM card A card mounted inside certain PCs to added an EM Area. EPROM Erasable programmable read-only memory; a type of ROM in which stored data can be erased, by ultraviolet light or other means, and reprogrammed.
Page 610 Glossary factory computer A general-purpose computer, usually quite similar to a business computer, that is used in automated factory control. FAL error An error generated from the user program by execution of an FAL(006) instruc- tion. FALS error An error generated from the user program by execution of an FALS(007) instruc- tion or an error generated by the system.
Page 611 Glossary holding area Words in memory designated to maintain status when the PC’s operating mode is changed or power is turned off and then back on. host interface An interface that allows communications with a host computer. Host Link System A system with one or more host computers connected to one or more PCs via Host Link Units or host interfaces so that the host computer can be used to trans- fer data to and from the PC(s).
Page 612 Glossary I/O Terminal A Remote I/O Unit connected in a Wired Remote I/O System to provide a limited number of I/O points at one location. There are several types of I/O Terminals. I/O Unit The most basic type of Unit mounted to a Backplane. I/O Units include Input Units and Output Units, each of which is available in a range of specifications.
Page 613 Glossary instruction block A group of instructions that is logically related in a ladder-diagram program. A logic block includes all of the instruction lines that interconnect with each other from one or more line connecting to the left bus bar to one or more right-hand instructions connecting to the right bus bar.
Page 614 Glossary ladder instruction An instruction that represents the conditions on a ladder-diagram program. The other instructions in a ladder diagram fall along the right side of the diagram and are called terminal instructions. least-significant (bit/word) See rightmost (bit/word) . Acronym for light-emitting diode; a device used as for indicators or displays. leftmost (bit/word) The highest numbered bits of a group of bits, generally of an entire word, or the highest numbered words of a group of words.
Page 615 Glossary megabyte A unit of storage equal to one million bytes. memory area Any of the areas in the PC used to hold data or programs. memory card A data storage media similar to a floppy disk. message number A number assigned to a message generated with the MSG(195) instruction. mnemonic code A form of a ladder-diagram program that consists of a sequential list of the in- structions without using a ladder diagram.
Page 616 Glossary OFF delay The delay between the time when a signal is switched OFF (e.g., by an input device or PC) and the time when the signal reaches a state readable as an OFF signal (i.e., as no signal) by a receiving party (e.g., output device or PC). offset A positive or negative value added to a base value such as an address to specify a desired value.
Page 617 Glossary overwrite Changing the content of a memory location so that the previous content is lost. Parameter Area A part of System DM used to designate various PC operating parameters. Parameter Backup Area A part of System DM used to back up the Parameter Area. parity Adjustment of the number of ON bits in a word or other unit of data so that the total is always an even number or always an odd number.
Page 618 Glossary grammable Controllers are used to automate control of external devices. Al- though single-unit Programmable Controllers are available, building-block Pro- grammable Controllers are constructed from separate components. Such Pro- grammable Controllers are formed only when enough of these separate compo- nents are assembled to form a functional assembly, i.e., there is no one individu- al Unit called a PC.
Page 619 Glossary An acronym for reliability, assurance, safety. read-only area A memory area from which the user can read status but to which data cannot be written. refresh The process of updating output status sent to external devices so that it agrees with the status of output bits held in memory and of updating input bits in memory so that they agree with the status of inputs from external devices.
Page 620 Glossary rising edge The point where a signal actually changes from an OFF to an ON status. Read only memory; a type of digital storage that cannot be written to. A ROM chip is manufactured with its program or data already stored in it and can never be changed.
Page 621 The arrangement in which Units in a System are connected. This term refers to the conceptual arrangement and wiring together of all the devices needed to comprise the System. In OMRON terminology, system configuration is used to describe the arrangement and connection of the Units comprising a Control Sys- tem that includes one or more PCs.
Page 622 Unit In OMRON PC terminology, the word Unit is capitalized to indicate any product sold for a PC System. Though most of the names of these products end with the word Unit, not all do, e.g., a Remote Terminal is referred to in a collective sense...
Page 623 Glossary unit address A number used to control network communications. Unit addresses are com- puted for Units in various ways, e.g., 10 hex is added to the unit number to deter- mine the unit address for a CPU Bus Unit. unit number A number assigned to some Link Units, Special I/O Units, and CPU Bus Units to facilitate identification when assigning words or other operating parameters.
Page 624: Index
Index clock, 49 adding to clock time, 350 compensation, 353 acronym, definition, 36 subtracting from clock time, 352 actions, maximum number, 24 clock pulse bits, 66 address tracing. See tracing commands, delivering commands through a network, 420 addresses compatibility, C–CV Series, 9 data area, description, 36 complements, calculating, 347–348 memory, description, 36...
Page 625 Index CPU Bus Units data conversion table, 593 definition, 47 data files disabling service, 57, 468 reading from Memory Card, 28, 396 Duplication Error Flags, 61 writing to Memory Card, 28, 398 Error Flags, 61, 63 Data Link Area, 50 I/O allocation, 47 Initializing Flags, 58 Data Registers, 70...
Page 626 Index execution condition, definition, 76 Execution Time Measured Flag, 56, 395 FAL Flag, 63 execution time, instructions, 472–485 FALS Flag, 60 Expansion CPU Rack, 32 File Missing Flag, 60 First Cycle Flag, 65 Expansion Data Memory Unit. See EM Unit GR, 65 Expansion I/O Rack, 32 I/O Bus Error Flag, 61...
Page 627 Index Index Registers, 70 copying current contents, 368 loading data, 367 GPC, 7 indirect addressing GPC (Graphics Programming Console), 7 BCD (in DM or EM), 116 binary (in DM or EM), 117 GR. See flags, GR DM and EM Areas, 69 Graphics Programming Console, 7 with Index and Data Registers, 70 input bits...
Page 628 Index CCS(173), 367 IF<002> NOT, 440 CJP(221), 138 IL(002), 90, 134–136 ILC(003), 90, 134–136 CJPN(222), 138 INBL(096), 317 CLC(079), 250 INC(090), 314 CLI(154), 386 INCB(092), 315 CMND(194), 420, 423 INCL(094), 316 CMP(020), 205 input comparison instructions (300 to 328), 213 CMP(028), 217 IODP(189), 362 CMPL(021), 207...
Page 629 Index OR NOT, 78, 122 TRSM(170), 393 ORW(131), 342 TSR(124), 435 ORWL(135), 345 TST(350), 124 OUT, 79, 126 TSTN(351), 124 OUT NOT, 79, 126 TSW(125), 436 PID(270), 330 TTIM(120), 148 PUSH(161), 390 UP(018), 123 RAD(458), 303 WAIT<005>, 443 RD2(280), 406 READ(190), 404 WDT(178), 361 RECV(193), 418, 423...
Page 630 Index interrupts, 377, 382 clearing, 386 masking, 385 macros, 380 power OFF, 383 manuals, 8 power OFF interrupt, 459, 461 CV-series, 8 power ON, 383 priority, 383 mathematics reading mask status, 388 See also trigonometric functions refresh servicing adding a range of words, 322 in asynchronous operation, 466 BCD calculation instructions, 274, 281, 287, 291 in synchronous operation, 468...
Page 631 Index non-fatal operating errors, 505 power interruption, 458 automatic restart following. See restart continuation normally closed condition, definition, 75 momentary, 460 number since start-up, 57 normally open condition, definition, 75 time of occurrence, 56, 460 NOT, definition, 75 precautions general, xiii operand data areas, 115 programming, 98, 102 zero-cross refreshing, 457...
Page 632 Index switches DIP. See DIP switch Memory Card power, 23 scan times. See cycle times scheduled refreshing, 456 synchronous operation, 455, 467 I/O response time, example, 489, 492 self-maintaining bits, using KEEP(011), 133 seven-segment displays, converting data, 231 SYSMAC BUS Remote I/O System, 13 disabling read/write access, 413 SFC control instructions, 427 disabling refreshing, 57, 468...
Page 633 Index timers, 67, 139 block programs, 447 changing step timers, 436 UN. See flags, underflow conditions when reset TIM, 143 Units TIM(015), 147 changing configuration, 44 TIML(121), 150 definition, 4 TTIM(120), 149 determining requirements, 6 example using CMP(020), 206 I/O Units, definition, 4 extended timers, 144 Link Units, definition, 4 flicker bits, 146...
Page 634: Revision History
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W202-E1-5 Revision code The following table outlines changes made to the manual. Page numbers refer to the previous version. Revision code Date Revised content...
Page 635 Revision History Revision code Date Revised content March 1993 CV2000, CVM1, and Personal Computer Unit added. Page 18: Program area capacity corrected in tables. Page 36: Notes concerning Units mounted to Slave Racks and use of Intelligent I/O Read/Write instructions corrected. Page 116: Description of refreshing of Completion Flags corrected.
Page 636 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Omron CV500-BC051 CV500-BI111 CV500-BI112 CV500-BI042 CV500-BC031 CV500-BI062 CV500-BC101...

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