Omron SYSMAC CV Series Operation Manual page 395

Interrupt Control
Interrupt Priority Levels
For each Interrupt Input Unit, bits 00 through 07 may be used for interrupt sig-
nals. Bits 08 through 15 are not used. When one of the bits assigned to an Inter-
rupt Input Unit turns ON, the interrupt program associated with it is called and
executed. A unique interrupt program number is associated with each bit ac-
cording to the following table.
Interrupt Input Unit
Unit no. Bit no.
0 0
1
2
3
4
5
6
7
1 0
1
2
3
4
5
6
7
A scheduled interrupt is repeated at regular intervals.
The time interval between interrupts is set by the user and is unrelated to the
cycle timing of the PC. The time interval can be set between 10 and 99,990 ms.
This capability is useful for periodic supervisory or executive program execution.
A power OFF interrupt is generated by an interruption of power to the CPU
longer than the momentary power interruption time set in the PC Setup (0 to
9 ms).
If the PC Setup (Execution controls 2) has been preset to enable power OFF
interrupts, the interrupt program is activated to manage the power outage.
The length of the power OFF interrupt program is limited. Refer to 6-1-6 Power
OFF Interruption and Restart Continuation for details.
A power ON interrupt is activated when power returns to the CPU after an inter-
ruption. The power ON interrupt is effective only if there is a power ON interrupt
program. The power ON interrupt program is executed after initialization.
The PC employs a priority system for handling interrupts. A power OFF interrupt
is given the highest priority, followed by power ON, scheduled, and I/O inter-
rupts, in that order. Lower numbered I/O interrupts are given priority over a high-
er numbered I/O interrupts.
In the CV1000, CV2000, CVM1-CPU11-EV2, or CVM1-CPU21-EV2 a level 0
scheduled interrupt (defined by setting N=4 in MSKS(153)) takes priority over a
level 1 scheduled interrupt (defined by setting N=5 when MSKS(153)). If a level
0 scheduled interrupt occurs while a level 1 scheduled interrupt is being ex-
ecuted, the level 1 scheduled interrupt program is halted until the level 0 sched-
uled interrupt is completed.
The I/O interrupt setting in the PC Setup determines whether I/O interrupts with
higher priority will be serviced immediately (interrupting the I/O interrupt pro-
gram currently being executed) or wait until the current I/O interrupt is com-
pleted.
Program Interrupt Input Unit
Unit no.
00 2
01
02
03
04
05
06
07
08 3
09
10
11
12
13
14
15
Section 5-31
Program
Bit no.
0 16
1 17
2 18
3 19
4 20
5 21
6 22
7 23
0 24
1 25
2 26
3 27
4 28
5 29
6 30
7 31
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