Branching Instruction Lines; Coding Multiple Right-Hand Instructions - Omron SYSMAC CV Series Operation Manual

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Branching Instruction Lines

Block a
000000
000001
LD
000000
AND
000001
000500
OR
000002
AND
AND NOT 000003

4-4-2 Coding Multiple Right-hand Instructions

0000
0000
00
03
0000
01
0000
02
0002
00
4-5

Branching Instruction Lines

The first logic block instruction is used to combine the execution conditions re-
sulting from blocks a and b, and the second one is to combine the execution
condition of block c with the execution condition resulting from the normally
closed condition assigned CIO 000003. The rest of the diagram can be coded
with OR, AND, and AND NOT instructions. The logical flow for this and the re-
sulting code are shown below.
Block b
001000
001001
LD
001000
AND
001001
OR LD
000004
LD
000500
AND
000003
000006
000002
OR
AND LD
000500
If there is more than one right-hand instruction executed with the same execu-
tion condition, they are coded consecutively following the last condition on the
instruction line. In the following example, the last instruction line contains one
more condition that corresponds to an AND with CIO 000400.
0004
00
When an instruction line branches into two or more lines, it is sometimes neces-
sary to use either interlocks or TR bits to maintain the execution condition that
existed at a branching point. This is because instruction lines are executed
across to a right-hand instruction before returning to the branching point to
execute instructions one a branch line. If a condition exists on any of the instruc-
tion lines after the branching point, the execution condition could change during
this time making proper execution impossible. The following diagrams illustrate
Block c
000005
000004
000005
000006
Address Instruction
0000
01
00000
00001
0005
00
00002
00003
0005
06
00004
00005
00006
00007
00008
Section 4-5
Address Instruction Operands
00000
LD
000000
00001
AND
000001
00002
LD
001000
00003
AND
001001
00004
OR LD
––
00005
OR
000500
00006
AND
000002
00007
AND NOT
000003
00008
LD
000004
00009
AND
000005
00010
OR
000006
00011
AND LD
––
00012
OUT
000500
Operands
LD
000000
OR
000001
OR
000002
OR
000200
AND
000003
OUT
000001
OUT
000500
AND
000400
OUT
000506
87

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