Omron SYSMAC CV Series Operation Manual page 479

Cycle Time
Interrupt Processing
Process
I/O interrupts I/O interrupt programs started with receipt
of interrupts from Interrupt Input Units.
Scheduled Scheduled interrupt program(s) started at
interrupt preset interval(s).
TIMH(015) Updates the PVs of high-speed timers in
refreshing the program every 10 ms.
Timer Updates the PVs of all timers in the
refreshing program every 80 ms if the cycle time
exceeds 80 ms.
I/O bus check Checks the I/O bus on the CPU,
Expansion CPU, and Expansion I/O
Racks
SYSMAC NET The data link words allocated to SYSMAC
Link refreshing NET Link Units are refreshed.
Interrupt processing can occur as often as
once each cycle.
SYSMAC LINK The data link words allocated to SYSMAC
refreshing LINK Units are refreshed.
Interrupt processing can occur as often as
once each cycle.
SYSMAC Masters receive I/O data from Slaves.
BUS/2
refreshing
CPU Bus Link Data in the CPU Bus Link Area is
refreshing refreshed.
Service Disable Bits
6-2-3 Operations Significantly Increasing Cycle Time
Operation Effect on cycle time
Instruction trace Cycle time increased 3 to
5 times.
468
Depending on the program, the following interrupt processes might be executed
in addition to the processes detailed in the table above. The actual cycle time is
the sum of the cycle time calculated in the table above and the time required for
the processes in the table below.
Actions
The Service Disable Bits shown in the table below are primarily used during syn-
chronous operation to reduce the cycle time; they are only effective in RUN and
MONITOR modes. The bits are OFF when the PC is first turned on, and are nor-
mally turned ON from the program.
Do not leave Service Disable Bits ON for longer than is necessary; service be-
tween the PC and the designated Unit will be stopped completely as long as the
corresponding Service Disable Bit is ON.
Word(s) Bit(s)
A015 00 to 15
A017 03
04
05
The instruction trace operation described below can significantly affect the cycle
time when performed from CVSS/SSS.
The cycle time will change during an instruction trace and high-speed
input signals might not be detected.
Set the maximum cycle time in the PC Setup at least 5 times higher
than its usual value.
Processing time
CV500/CVM1-CPU01-EV2
Depends on the I/O interrupt programs.
Depends on the scheduled interrupt program(s).
µ µ
12 s + 0.8 s per timer
µ µ
10 s + 1.1 s per timer
µ
0.6 s every 20 ms
µ
Approx. 1.4 ms + 1 s per data link word, add 0.3 ms if
both DM and CIO are used for data links.
µ
Approx. 1.4 ms + 1 s per data link word, add 0.3 ms if
both DM and CIO are used for data links.
µ
Approx. 2.0 ms plus 1 s per word refreshed
0.8 ms every 10 ms (when the PC is set to use the CPU
Bus Link Area in the PC Setup)
CPU Bus Service Disable Bits (Bits 00 to 15
correspond to units #0 to #15.)
Host Link/NT Link Service Disable Bit
Peripheral Service Disable Bit
I/O Refresh Disable Bit
Precautions
Section 6-2
CV1000/2000/
CVM1-CPU11/21-EV2
µ µ
10 s + 0.7 s per timer
µ µ
8 s + 0.9 s per timer
Function