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S5-115U Manual
9
Interrupt Processing
In this chapter you will learn the following:
•
Which blocks are designed for handling process interrupts in the S5-115U
•
How a process interrupt is intitiated
•
What happens "internally" during interrupt processing
•
The important points about simultaneous use of timed interrupts (timed-interrupt OBs)
•
How to calculate the response times to a process interrupt.
In addition, Section 9.3 shows how to start up the 434-7 digital input module (with process
interrupt).
9.1
Programming Interrupt Blocks
You can use interrupt-initiating modules in the S5-115U (e.g. signal preprocessing modules or the
434-7 digitial input module). These modules activate the CPU over an interrupt line in the I/O bus
(S5 backplane bus). The CPU distinguishes between A, B, C or D interrupts depending on which
interrupt line has been activated.
Each of these interrupts causes the operating system of the CPU to interrupt the cyclic or time-
controlled program and to call an interrupt OB:
OB2 in the case of interrupt A (interrupt A is triggered by the 434-7 DI module, by some CPs or by
IPs)
OB3 in the case of interrupt B (interrupt B is triggered by some CPs or by IPs)
OB4 in the case of interrupt C (interrupt C is triggered by some CPs or by IPs)
OB5 in the case of interrupt D (interrupt D is triggered by some CPs or by IPs)
What Interrupts What and Where?
As soon as the current cycle has been interrupted, i.e. while the CPU is processing an interrupt OB,
further interrupts are automatically disabled. A running interrupt program can therefore not be
interrupted.
If several interrupts are pending simultaneously, the priority is determined as follows:
Highest priority:
Lowest priority:
Interrupts A to D have higher priority than timed interrupts (OB10 to 13). The priority of OB6 in
relation to interrupts A to D can be programmed (see Section 7.4.4).
An interrupt A, B, C or D interrupts the cyclic or time-controlled program after each operation.
Exception: the TNB operation can be interrupted after every word in the case of CPUs 941, 942
and 943. The execution time of the TNB operation in the case of CPU 944 is so short that
interruptibility has been dispensed with.
Integral function blocks and operating system routines can only be interrupted at specified points
by an interrupt A (B, C, D) (cannot be influenced!).
If you have not programmed an interrupt OB, the cyclic or time-controlled program will continue
immediately after the interrupt. If further interrupts occur during interrupt processing (edge is
enough!), the CPU stores one of these interrupts per interrupt line! Prerequisite for detecting
another interrupt is that the interrupt-initiating edges are separated by an interval of at least
12 µs! The subsequent order of processing the interrupts follows the interrupt priority described
above.
EWA 4NEB 811 6130-02b
Interrupt A
Interrupt B
Interrupt C
Interrupt D
Interrupt Processing
9-1
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