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S5-115U Manual
Conditon Code Generation for Shift Operations
Execution of shift operations sets CC 0 and CC 1. It does not affect the overflow condition code
(see Table 8-35).
Code setting depends on the state of the last bit shifted out.
Table 8-35. Condition Code Settings for Shift Operations
Value of
the Last Bit
Shifted Out
"0"
"1"
Condition Code Generation for Conversion Operations
The formation of the two's complement (CSW) sets all condition codes (see Table 8-36). The state
of the condition codes is based on the result of the conversion function.
Table 8-36. Condition Code Settings for Conversion Operations
Result after
Arithmetic Operation
is Executed
*
- 32768
- 32767 to - 1
0
+1 to +32767
* This number is the result of the conversion of KH=8000.
EWA 4NEB 811 6130-02b
Condition Codes
CC 1
CC 0
0
0
1
0
Condition Codes
CC 1
CC 0
0
1
0
1
0
0
1
0
STEP 5 Operations
Possible
Jump Operations
OV
JZ
JN, JP
Possible
Jump Operations
OV
1
JN, JM, JO
0
JN, JM
0
JZ
0
JN, JP
8-75
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