Table of Contents
Advertisement
S5-115U Manual
Control signals
Address bus
Address decoder
+24 V
+16 V
+5.6 V -7.2 V
Switched-
mode
regulator
L+
L –
MUX
Multiplexer
D/A
Digital-analog converter
Figure 10-26. Block Diagram with Signal Interchange between
EWA 4NEB 811 6130-02b
CPU
Control signal
Processor
Data
Circulating buffer
Optocoupler
D
MUX
Sample and Hold
U
A0
A0
U
I
CPU and a 470 Analog Output Module
Analog Value Processing
S5 bus
Data bus
Clock pulse
Counter
Galvanic isolation
Digital-analog converter
A
Multiplexer
Sample and Hold
8×
V/I converter
8×
Process signal
A7
U
output
U
A7
I
10-55
Advertisement
Table of Contents
