Segger J-Link User Manual page 210

210
8.3.1.3 Debugging on Cortex-M3 devices
The RDI protocol has only been specified by ARM for ARM 7/9 cores. For Cortex-M
there is no official extension of the RDI protocol regarding the register assignement,
that has been approved by ARM. Since IAR EWARM version 5.11 it is possible to use
J-Link RDI for Cortex-M devices because SEGGER and IAR have been come to an
agreement regarding the RDI register assignment for Cortex-M. The following table
lists the register assignment for RDI and Cortex-M:
Register
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
22
23
24
25
26
27
28
Table 8.1: Cortex-M register mapping for IAR + J-Link RDI
J-Link / J-Trace (UM08001)
CHAPTER 8
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
MSP / PSP (depending on mode)
R14 (LR)
R15 (PC)
XPSR
APSR
IPSR
EPSR
IAPSR
EAPSR
IEPSR
PRIMASK
FAULTMASK
BASEPRI
BASEPRI_MAX
CFBP (CONTROL/FAULT/BASEPRI/PRIMASK)
Assigned register
© 2004-2013 SEGGER Microcontroller GmbH & Co. KG
RDI