Stm32F4Xxx - Segger J-Link User Manual

9.15.4 STM32F4xxx

These device are Cortex-M4 based.
All devices of this family are supported by J-Link.
9.15.4.1 ETM init
The following sequence can be used to prepare STM32F4xxx devices for 4-bit ETM
tracing:
int v;
//
// Enable GPIOE clock
//
*((volatile int *)(0x40023830)) = 0x00000010;
//
// Assign trace pins to alternate function in order
// to make them usable as trace pins
// PE2: Trace clock
// PE3: TRACE_D0
// PE4: TRACE_D1
// PE5: TRACE_D2
// PE6: TRACE_D3
//
*((volatile int *)(0x40021000)) = 0x00002AA0;
//
// DBGMCU_CR, enable trace I/O and configure pins for 4-bit trace.
//
v = *((volatile int *)(0xE0042004));
v &= ~(7 << 5); // Preserve all bits except the trace pin configuration
v |= (7 << 5); // Enable trace I/O and configure pins for 4-bit trace
*((volatile int *)(0xE0042004)) = v;
9.15.4.2 Debugging with software watchdog enabled
If the device shall be debugged with one of the software watchdogs (independed
watchdog / window watchdog) enabled, there is an additional init step necessary to
make the watchdog counter stop when the CPU is halted by the debugger. This is
configured in the DBGMCU_APB1_FZ register. The following sequence can be used to
enable debugging with software watchdogs enabled:
//
// Configure both watchdog timers to be halted if the CPU is halted by the debugger
//
*((volatile int *)(0xE0042008)) |= (1 << 11) | (1 << 12);
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